pcifuction_haero.h

一个 PCI 驱动,实现PC 机与 PCI9045 的通信

#include <windows.h>

/**********************************************
*               Globals
*
**********************************************/
HANDLE       GL_hDevice;
HANDLE       hMutexGlobalData;     // Mutex for global variable protection

/******************************************
 * Basic Type Definitions
 ******************************************/
#define API_RETURN_CODE_STARTS      0x200 
#define FIND_AMOUNT_MATCHED         80001
#define PLX_RESET_EMBED_INT         ((unsigned long)(1 << 31))
#define MAX_PLX_DRIVERS             7       // Total number of PLX drivers
#define AssertBLAST                 0
#define EOTAsserted                 1
#define MAX_DMA_CHANNELS            4       // Max number of DMA channels for a device
#define MAX_DMA_TIMEOUT             1000    // Max timeout in milliseconds for DMA transfer

#define UnlockGlobals()  {if (hMutexGlobalData != NULL){ReleaseMutex(hMutexGlobalData);}}
#define LockGlobals()    {if (hMutexGlobalData != NULL){WaitForSingleObject(hMutexGlobalData,INFINITE);}}

typedef enum _RETURN_CODE
{
    ApiSuccess = API_RETURN_CODE_STARTS,
    ApiFailed,
    ApiAccessDenied,
    ApiDmaChannelUnavailable,
    ApiDmaChannelInvalid,
    ApiDmaChannelTypeError,
    ApiDmaInProgress,
    ApiDmaDone,
    ApiDmaPaused,
    ApiDmaNotPaused,
    ApiDmaCommandInvalid,
    ApiDmaManReady,
    ApiDmaManNotReady,
    ApiDmaInvalidChannelPriority,
    ApiDmaManCorrupted,
    ApiDmaInvalidElementIndex,
    ApiDmaNoMoreElements,
    ApiDmaSglInvalid,
    ApiDmaSglQueueFull,
    ApiNullParam,
    ApiInvalidBusIndex,
    ApiUnsupportedFunction,
    ApiInvalidPciSpace,
    ApiInvalidIopSpace,
    ApiInvalidSize,
    ApiInvalidAddress,
    ApiInvalidAccessType,
    ApiInvalidIndex,
    ApiMuNotReady,
    ApiMuFifoEmpty,
    ApiMuFifoFull,
    ApiInvalidRegister,
    ApiDoorbellClearFailed,
    ApiInvalidUserPin,
    ApiInvalidUserState,
    ApiEepromNotPresent,
    ApiEepromTypeNotSupported,
    ApiEepromBlank,
    ApiConfigAccessFailed,
    ApiInvalidDeviceInfo,
    ApiNoActiveDriver,
    ApiInsufficientResources,
    ApiObjectAlreadyAllocated,
    ApiAlreadyInitialized,
    ApiNotInitialized,
    ApiBadConfigRegEndianMode,
    ApiInvalidPowerState,
    ApiPowerDown,
    ApiFlybyNotSupported,
    ApiNotSupportThisChannel,
    ApiNoAction,
    ApiHSNotSupported,
    ApiVPDNotSupported,
    ApiVpdNotEnabled,
    ApiNoMoreCap,
    ApiInvalidOffset,
    ApiBadPinDirection,
    ApiPciTimeout,
    ApiDmaChannelClosed,
    ApiDmaChannelError,
    ApiInvalidHandle,
    ApiBufferNotReady,
    ApiInvalidData,
    ApiDoNothing,
    ApiDmaSglBuildFailed,
    ApiPMNotSupported,
    ApiLastError            /* do not add API errors below this line */
} RETURN_CODE, *PRETURN_CODE;

typedef union _DMA_TRANSFER_ELEMENT
{
    struct
    {

        union
        {
            unsigned long LowPciAddr;
            unsigned long UserAddr;
        };
        unsigned long IopAddr;
        unsigned long TransferCount;
        unsigned long PciSglLoc         :1;
        unsigned long LastSglElement    :1;
        unsigned long TerminalCountIntr :1;
        unsigned long IopToPciDma       :1;
        unsigned long NextSglPtr        :28;
        unsigned long HighPciAddr;
    } Pci9054Dma;
    unsigned long Reserved[12];
} DMA_TRANSFER_ELEMENT, *PDMA_TRANSFER_ELEMENT;

typedef struct _VIRTUAL_ADDRESSES
{
    unsigned long Va0;
    unsigned long Va1;
    unsigned long Va2;
    unsigned long Va3;
    unsigned long Va4;
    unsigned long Va5;
    unsigned long VaRom;
} VIRTUAL_ADDRESSES, *PVIRTUAL_ADDRESSES;

typedef struct _DEVICE_LOCATION
{
    unsigned long DeviceId;
    unsigned long VendorId;
    unsigned long BusNumber;
    unsigned long SlotNumber;
    unsigned char SerialNumber[16];
} DEVICE_LOCATION, *PDEVICE_LOCATION;

typedef struct _PCI_MEMORY
{
    unsigned long UserAddr;
    unsigned long PhysicalAddr;
    unsigned long Size;
} PCI_MEMORY, *PPCI_MEMORY;


typedef struct _MANAGEMENTDATA
{
    RETURN_CODE         ReturnCode;
    unsigned long       CfgRegNumber;
    unsigned long       Value;
    DEVICE_LOCATION     Device;
    VIRTUAL_ADDRESSES   VirtAddr;
    HANDLE              UserProcessId;
    PCI_MEMORY          PciMemory;
} MANAGEMENTDATA;

typedef enum _MAILBOX_ID
{
    MailBox0,
    MailBox1,
    MailBox2,
    MailBox3,
    MailBox4,
    MailBox5,
    MailBox6,
    MailBox7
} MAILBOX_ID, *PMAILBOX_ID;

/* Register Operations parameters */
typedef struct _REGISTERDATA
{
    RETURN_CODE    ReturnCode;
    unsigned long  RegOffset;
    unsigned long  Count;
    unsigned long  Data;
    MAILBOX_ID     MailboxId;
} REGISTERDATA;

typedef enum _IOP_SPACE
{
    IopSpace0,
    IopSpace1,
    IopSpace2,
    IopSpace3,
    MsLcs0,
    MsLcs1,
    MsLcs2,
    MsLcs3,
    MsDram,
    MsDefault,
    ExpansionRom
} IOP_SPACE, *PIOP_SPACE;

/* Access Size Type */
typedef enum _ACCESS_TYPE
{
    BitSize8,
    BitSize16,
    BitSize32,
    BitSize64
} ACCESS_TYPE, *PACCESS_TYPE;


/*  Bus Memory and IOP transactions parameters */
typedef struct _BUSIOPDATA
{
    RETURN_CODE     ReturnCode;
    IOP_SPACE       IopSpace;
    unsigned long   Address;
    BOOLEAN         Remap;
    unsigned long   Data;
    unsigned long   TransferSize;
    ACCESS_TYPE     AccessType;
    unsigned char   ByteBuffer;
    unsigned short  ShortBuffer;
    unsigned long   LongBuffer;
} BUSIOPDATA;

/* DMA Channel Priority Definitions */
typedef enum _DMA_CHANNEL_PRIORITY
{
    Channel0Highest,
    Channel1Highest,
    Channel2Highest,
    Channel3Highest,
    Rotational
} DMA_CHANNEL_PRIORITY;

/* DMA Channel Descriptor Structure */  
typedef struct _DMA_CHANNEL_DESC 
{
    unsigned long EnableReadyInput         :1;
    unsigned long EnableBTERMInput         :1;
    unsigned long EnableIopBurst           :1;
    unsigned long EnableWriteInvalidMode   :1;
    unsigned long EnableDmaEOTPin          :1;
    unsigned long DmaStopTransferMode      :1;
    unsigned long HoldIopAddrConst         :1;
    unsigned long HoldIopSourceAddrConst   :1;
    unsigned long HoldIopDestAddrConst     :1;
    unsigned long DemandMode               :1;
    unsigned long SrcDemandMode            :1;
    unsigned long DestDemandMode           :1;
    unsigned long EnableTransferCountClear :1;
    unsigned long WaitStates               :4;
    unsigned long IopBusWidth              :2;
    unsigned long EOTEndLink               :1;
    unsigned long ValidStopControl         :1;
    unsigned long ValidModeEnable          :1;
    unsigned long EnableDualAddressCycles  :1;
    unsigned long Reserved1                :9;
    unsigned long TholdForIopWrites        :4;
    unsigned long TholdForIopReads         :4;
    unsigned long TholdForPciWrites        :4;
    unsigned long TholdForPciReads         :4;
    unsigned long EnableFlybyMode          :1;
    unsigned long FlybyDirection           :1;
    unsigned long EnableDoneInt            :1;
    unsigned long Reserved2                :13;
    DMA_CHANNEL_PRIORITY DmaChannelPriority;
} DMA_CHANNEL_DESC, *PDMA_CHANNEL_DESC;

typedef enum _DMA_CHANNEL
{
    IopChannel0,
    IopChannel1,
    IopChannel2,
    PrimaryPciChannel0,
    PrimaryPciChannel1,
    SecondaryPciChannel0,
    SecondaryPciChannel1
} DMA_CHANNEL, *PDMA_CHANNEL;

/* DMA Transfer Direction Type */
typedef enum _DMA_DIRECTION
{
    IopToIop,
    IopToPrimaryPci,
    PrimaryPciToIop,
    IopToSecondaryPci,
    SecondaryPciToIop,
    PrimaryPciToSecondaryPci,
    SecondaryPciToPrimaryPci
} DMA_DIRECTION, *PDMA_DIRECTION;

/* DMA Command Definitions */
typedef enum _DMA_COMMAND
{
    DmaStart,
    DmaPause,
    DmaResume,
    DmaAbort,
    DmaStatus
} DMA_COMMAND, *PDMA_COMMAND;

/* DMA transaction parameters */
typedef struct _DMADATA
{
    RETURN_CODE             ReturnCode;
    unsigned long           SourceAddrs;
    unsigned long           DestAddrs;
    unsigned long           TransferSize;
    DMA_TRANSFER_ELEMENT    TransBlock1;
    DMA_CHANNEL_DESC        DmaChannelDesc;
    DMA_CHANNEL             DmaChannel;
    DMA_DIRECTION           DmaDirection;
    DMA_COMMAND             DmaCommand;
    BOOLEAN                 ReturnImmediate;
} DMADATA;

/* PLX Interrupt Structure */   
typedef struct _PLX_INTR
{
    unsigned long InboundPost      :1;
    unsigned long OutboundPost     :1;
    unsigned long OutboundOverflow :1;
    unsigned long OutboundOption   :1;
    unsigned long IopDmaChannel0   :1;
    unsigned long PciDmaChannel0   :1;
    unsigned long IopDmaChannel1   :1;
    unsigned long PciDmaChannel1   :1;
    unsigned long IopDmaChannel2   :1;
    unsigned long PciDmaChannel2   :1;
    unsigned long Mailbox0         :1;
    unsigned long Mailbox1         :1;
    unsigned long Mailbox2         :1;
    unsigned long Mailbox3         :1;
    unsigned long Mailbox4         :1;
    unsigned long Mailbox5         :1;
    unsigned long Mailbox6         :1;
    unsigned long Mailbox7         :1;
    unsigned long IopDoorbell      :1;
    unsigned long PciDoorbell      :1;
    unsigned long SerialPort1      :1;
    unsigned long SerialPort2      :1;
    unsigned long BIST             :1;
    unsigned long PowerManagement  :1;
    unsigned long PciMainInt       :1;
    unsigned long IopToPciInt      :1;
    unsigned long IopMainInt       :1;
    unsigned long PciAbort         :1;
    unsigned long PciReset         :1;
    unsigned long PciPME           :1;
    unsigned long Enum             :1;
    unsigned long PciENUM          :1;
    unsigned long IopBusTimeout    :1;
    unsigned long AbortLSERR       :1;
    unsigned long ParityLSERR      :1;
    unsigned long RetryAbort       :1;
    unsigned long LocalParityLSERR :1;
    unsigned long PciSERR          :1;
    unsigned long IopRefresh       :1;
    unsigned long PciINTApin       :1;
    unsigned long IopINTIpin       :1;
    unsigned long TargetAbort      :1;
    unsigned long Ch1Abort         :1;
    unsigned long Ch0Abort         :1;
    unsigned long DMAbort          :1;
    unsigned long IopToPciInt_2    :1;
    unsigned long SwInterrupt      :1;
    unsigned long Reserved         :17;
} PLX_INTR, *PPLX_INTR;

/* Power State Definitions */
typedef enum _PLX_POWER_LEVEL
{
    D0Uninitialized,
    D0,
    D1,
    D2,
    D3Hot,
    D3Cold
} PLX_POWER_LEVEL, *PPLX_POWER_LEVEL;

/* EEPROM Type Definitions */
typedef enum _EEPROM_TYPE
{
    Eeprom93CS46,
    Eeprom93CS56,
    Eeprom93CS66,
    EepromX24012,
    EepromX24022,
    EepromX24042,
    EepromX24162,
    EEPROM_UNSUPPORTED
} EEPROM_TYPE, *PEEPROM_TYPE;

/* USER Pin Definitions */
typedef enum _USER_PIN
{
    USER0,
    USER1,
    USER2,
    USER3,
    USER4,
    USER5
} USER_PIN, *PUSER_PIN;

/* USER Pin Values */
typedef enum _PLX_PIN_STATE
{
    Inactive,
    Active
} PLX_PIN_STATE, *PPLX_PIN_STATE;

/* This structure will hold all other datatypes */
typedef struct _MISCDATA
{
    PLX_INTR        IntrInfo;
    unsigned long   Value1;
    unsigned long   Value2;
    unsigned long   Value;
    PLX_POWER_LEVEL PlxPowerLevel;
    EEPROM_TYPE     EepromType;
    USER_PIN        UserPinNum;
    PLX_PIN_STATE   PinState;
    RETURN_CODE     ReturnCode;
    HANDLE          EventHandle;
} MISCDATA;


/*  Used to pass all arguments down to the driver */
typedef union _IOCTLDATA
{
    MANAGEMENTDATA MgmtData;
    REGISTERDATA   RegData;
    BUSIOPDATA     BusIopData;
    DMADATA        DmaData;
    MISCDATA       MiscData;
} IOCTLDATA;

typedef struct _IO_NODE
{
    IOCTLDATA        IoBuffer;                  // The pending I/O buffer
    OVERLAPPED       Overlapped;                // The pending Overlapped structure
    BOOLEAN          InUse;                     // Flag specifying whether the I/O is pending
    struct _IO_NODE *pNext;                     // Pointer to the next node in the list
} IO_NODE;

typedef struct _DEVICE_NODE
{
    HANDLE               Handle;                // Handle to the device driver
    VIRTUAL_ADDRESSES    VirtualAddrs;          // Virtual address mappings for the device
    PCI_MEMORY           PciMemory;             // Address of the common buffer
    IO_NODE             *pEventList;            // List of event handles
    IO_NODE             *pDmaList;              // List of DMA I/O buffers
    struct _DEVICE_NODE *pNext;                 // Pointer to next device in the list
} DEVICE_NODE;

unsigned char * PlxDrivers[] = 
{
    "Pci9080-0",
    "Pci9054-0",
    "Iop480-0",
    "Pci9030-0",
    "Pci9050-0",
    "Pci9656-0",
    "Pci9056-0"
};

#define DmaIndex(DmaChannel)     (DmaChannel - IopChannel2)
DEVICE_NODE *pDeviceList;  // Pointer to list of open devices and their resources
IO_NODE     *pIoPoolList;          // Pointer to the pool of allocated I/O nodes

unsigned char Pci_Open_Clos_Fuction(unsigned char way);
unsigned char SelectDevice( DEVICE_LOCATION *pDevice);
RETURN_CODE PlxPciDeviceOpen(DEVICE_LOCATION *pDevice,HANDLE *pDrvHandle);
RETURN_CODE PlxPciDeviceFind(DEVICE_LOCATION *pDevice,unsigned long *pRequestLimit);
DEVICE_NODE * DeviceListAdd(HANDLE hDevice);
IO_NODE *IoPoolGetNode(void);
void IoPoolReleaseNode(IO_NODE *pIoNode);
RETURN_CODE PlxPciDeviceClose(HANDLE hDevice);
BOOLEAN DeviceListRemove(HANDLE hDevice);
void IoListDestroy(IO_NODE **pIoList);
BOOLEAN IoListRemove(IO_NODE **pIoList,IO_NODE  *pIoNodeToRemove);
BOOLEAN Haero9054SglDma(BOOLEAN Direction,unsigned long LocalAddress,unsigned short  TransferCount,unsigned short DmaBuffer[]);
RETURN_CODE PlxChipTypeGet(HANDLE  hDevice,unsigned long  *pChipType,unsigned char *pRevision);
RETURN_CODE PlxDmaSglChannelOpen(HANDLE hDevice,DMA_CHANNEL dmaChannel,DMA_CHANNEL_DESC *pDmaChannelDesc);
RETURN_CODE PlxIntrAttach(HANDLE    hDevice,PLX_INTR  intrTypes,HANDLE   *pEventHdl);
RETURN_CODE PlxDmaSglTransfer(HANDLE  hDevice,DMA_CHANNEL dmaChannel,DMA_TRANSFER_ELEMENT *pDmaData,BOOLEAN  returnImmediate);
RETURN_CODE PlxDmaSglChannelClose(HANDLE hDevice,DMA_CHANNEL dmaChannel);
DEVICE_NODE *DeviceListFind(HANDLE hDevice);
BOOLEAN DmaListBuild(DEVICE_NODE *pDevice);
IO_NODE * DmaListGetNode(DEVICE_NODE *pDevice,unsigned char  index);
IO_NODE * IoListFindByEventHandle(IO_NODE *pIoList,HANDLE   hEvent);
IO_NODE * IoListAdd(IO_NODE **pIoList,HANDLE    hEvent);