📄 hw_sysctl.h
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#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601
#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608
#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616
#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671
#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793
#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93
#define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634
#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
#define SYSCTL_DID1_PRTNO_3826 0x00420000 // LM3S3826
#define SYSCTL_DID1_PRTNO_3J26 0x00410000 // LM3S3J26
#define SYSCTL_DID1_PRTNO_3N26 0x00400000 // LM3S3N26
#define SYSCTL_DID1_PRTNO_3W26 0x003F0000 // LM3S3W26
#define SYSCTL_DID1_PRTNO_3Z26 0x003E0000 // LM3S3Z26
#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
#define SYSCTL_DID1_PRTNO_5651 0x000C0000 // LM3S5651
#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
#define SYSCTL_DID1_PRTNO_5656 0x004D0000 // LM3S5656
#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732
#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737
#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739
#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791
#define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951
#define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956
#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91
#define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31
#define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36
#define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31
#define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36
#define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51
#define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56
#define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31
#define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36
#define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36
#define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611
#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618
#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790
#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792
#define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997
#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90
#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95
#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96
#define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97
#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
// to 70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
// (-40C to 85C)
#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
// to 105C)
#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
#define SYSCTL_DID1_PKG_QFN 0x00000018 // QFN package
#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
#define SYSCTL_DID1_PRTNO_S 16 // Part number shift
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
#define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present
#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present
#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
#define SYSCTL_DC1_MINSYSDIV_100 \
0x00001000 // Divide VCO (400MHZ) by 5 minimum
#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
// 6 minimum
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
// with a PLL divider of 4
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
// PLL divider of 8
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
// PLL divider of 10
#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
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