📄 memory.c
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value = address##type(ewram, address); \ break; \ \ case 0x03: \ /* internal work RAM */ \ value = address##type(iwram, (address & 0x7FFF) + 0x8000); \ break; \ \ case 0x04: \ /* I/O registers */ \ value = address##type(io_registers, address & 0x3FF); \ break; \ \ case 0x05: \ /* palette RAM */ \ value = address##type(palette_ram, address & 0x3FF); \ break; \ \ case 0x06: \ /* VRAM */ \ address &= 0x1FFFF; \ if(address > 0x18000) \ address -= 0x8000; \ \ value = address##type(vram, address); \ break; \ \ case 0x07: \ /* OAM RAM */ \ value = address##type(oam_ram, address & 0x3FF); \ break; \ \ case 0x08: \ case 0x09: \ case 0x0A: \ case 0x0B: \ case 0x0C: \ /* gamepak ROM */ \ if((address & 0x1FFFFFF) >= gamepak_size) \ { \ value = 0; \ } \ else \ { \ read_memory_gamepak(type); \ } \ break; \ \ case 0x0D: \ if((address & 0x1FFFFFF) < gamepak_size) \ { \ read_memory_gamepak(type); \ } \ else \ { \ value = read_eeprom(); \ } \ \ break; \ \ case 0x0E: \ case 0x0F: \ read_backup##type(); \ break; \ \ default: \ read_open##type(); \ break; \ } \#define trigger_dma(dma_number) \ if(value & 0x8000) \ { \ if(dma[dma_number].start_type == DMA_INACTIVE) \ { \ u32 start_type = (value >> 12) & 0x03; \ u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) & \ 0xFFFFFFF; \ \ dma[dma_number].dma_channel = dma_number; \ dma[dma_number].source_address = \ address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF; \ dma[dma_number].dest_address = dest_address; \ dma[dma_number].source_direction = (value >> 7) & 0x03; \ dma[dma_number].repeat_type = (value >> 9) & 0x01; \ dma[dma_number].start_type = start_type; \ dma[dma_number].irq = (value >> 14) & 0x01; \ \ /* If it is sound FIFO DMA make sure the settings are a certain way */ \ if((dma_number >= 1) && (dma_number <= 2) && \ (start_type == DMA_START_SPECIAL)) \ { \ dma[dma_number].length_type = DMA_32BIT; \ dma[dma_number].length = 4; \ dma[dma_number].dest_direction = DMA_FIXED; \ if(dest_address == 0x40000A4) \ dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B; \ else \ dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A; \ } \ else \ { \ u32 length = \ address16(io_registers, (dma_number * 12) + 0xB8); \ \ if((dma_number == 3) && ((dest_address >> 24) == 0x0D) && \ ((length & 0x1F) == 17)) \ { \ eeprom_size = EEPROM_8_KBYTE; \ } \ \ if(dma_number < 3) \ length &= 0x3FFF; \ \ if(length == 0) \ { \ if(dma_number == 3) \ length = 0x10000; \ else \ length = 0x04000; \ } \ \ dma[dma_number].length = length; \ dma[dma_number].length_type = (value >> 10) & 0x01; \ dma[dma_number].dest_direction = (value >> 5) & 0x03; \ } \ \ address16(io_registers, (dma_number * 12) + 0xBA) = value; \ if(start_type == DMA_START_IMMEDIATELY) \ return dma_transfer(dma + dma_number); \ } \ } \ else \ { \ dma[dma_number].start_type = DMA_INACTIVE; \ dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND; \ address16(io_registers, (dma_number * 12) + 0xBA) = value; \ } \#define access_register8_high(address) \ value = (value << 8) | (address8(io_registers, address)) \#define access_register8_low(address) \ value = ((address8(io_registers, address + 1)) << 8) | value \#define access_register16_high(address) \ value = (value << 16) | (address16(io_registers, address)) \#define access_register16_low(address) \ value = ((address16(io_registers, address + 2)) << 16) | value \cpu_alert_type function_cc write_io_register8(u32 address, u32 value){ switch(address) { case 0x00: { u32 dispcnt = io_registers[REG_DISPCNT]; if(value != (dispcnt & 0xFF)) oam_update = 1; address8(io_registers, 0x00) = value; break; } // DISPSTAT (lower byte) case 0x04: address8(io_registers, 0x04) = (address8(io_registers, 0x04) & 0x07) | (value & ~0x07); break; // VCOUNT case 0x06: case 0x07: break; // BG2 reference X case 0x28: access_register8_low(0x28); access_register16_low(0x28); affine_reference_x[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x28) = value; break; case 0x29: access_register8_high(0x28); access_register16_low(0x28); affine_reference_x[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x28) = value; break; case 0x2A: access_register8_low(0x2A); access_register16_high(0x28); affine_reference_x[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x28) = value; break; case 0x2B: access_register8_high(0x2A); access_register16_high(0x28); affine_reference_x[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x28) = value; break; // BG2 reference Y case 0x2C: access_register8_low(0x2C); access_register16_low(0x2C); affine_reference_y[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x2C) = value; break; case 0x2D: access_register8_high(0x2C); access_register16_low(0x2C); affine_reference_y[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x2C) = value; break; case 0x2E: access_register8_low(0x2E); access_register16_high(0x2C); affine_reference_y[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x2C) = value; break; case 0x2F: access_register8_high(0x2E); access_register16_high(0x2C); affine_reference_y[0] = (s32)(value << 4) >> 4; address32(io_registers, 0x2C) = value; break; // BG3 reference X case 0x38: access_register8_low(0x38); access_register16_low(0x38); affine_reference_x[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x38) = value; break; case 0x39: access_register8_high(0x38); access_register16_low(0x38); affine_reference_x[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x38) = value; break; case 0x3A: access_register8_low(0x3A); access_register16_high(0x38); affine_reference_x[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x38) = value; break; case 0x3B: access_register8_high(0x3A); access_register16_high(0x38); affine_reference_x[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x38) = value; break; // BG3 reference Y case 0x3C: access_register8_low(0x3C); access_register16_low(0x3C); affine_reference_y[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x3C) = value; break; case 0x3D: access_register8_high(0x3C); access_register16_low(0x3C); affine_reference_y[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x3C) = value; break; case 0x3E: access_register8_low(0x3E); access_register16_high(0x3C); affine_reference_y[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x3C) = value; break; case 0x3F: access_register8_high(0x3E); access_register16_high(0x3C); affine_reference_y[1] = (s32)(value << 4) >> 4; address32(io_registers, 0x3C) = value; break; // Sound 1 control sweep case 0x60: access_register8_low(0x60); gbc_sound_tone_control_sweep(); break; case 0x61: access_register8_low(0x60); gbc_sound_tone_control_sweep(); break; // Sound 1 control duty/length/envelope case 0x62: access_register8_low(0x62); gbc_sound_tone_control_low(0, 0x62); break; case 0x63: access_register8_high(0x62); gbc_sound_tone_control_low(0, 0x62); break; // Sound 1 control frequency case 0x64: access_register8_low(0x64); gbc_sound_tone_control_high(0, 0x64); break; case 0x65: access_register8_high(0x64); gbc_sound_tone_control_high(0, 0x64); break; // Sound 2 control duty/length/envelope case 0x68: access_register8_low(0x68); gbc_sound_tone_control_low(1, 0x68); break; case 0x69: access_register8_high(0x68); gbc_sound_tone_control_low(1, 0x68); break; // Sound 2 control frequency case 0x6C: access_register8_low(0x6C); gbc_sound_tone_control_high(1, 0x6C); break; case 0x6D: access_register8_high(0x6C); gbc_sound_tone_control_high(1, 0x6C); break; // Sound 3 control wave case 0x70: access_register8_low(0x70); gbc_sound_wave_control(); break; case 0x71: access_register8_high(0x70); gbc_sound_wave_control(); break; // Sound 3 control length/volume case 0x72: access_register8_low(0x72); gbc_sound_tone_control_low_wave(); break; case 0x73: access_register8_high(0x72); gbc_sound_tone_control_low_wave(); break; // Sound 3 control frequency case 0x74: access_register8_low(0x74); gbc_sound_tone_control_high_wave(); break; case 0x75: access_register8_high(0x74); gbc_sound_tone_control_high_wave(); break; // Sound 4 control length/envelope case 0x78: access_register8_low(0x78); gbc_sound_tone_control_low(3, 0x78); break; case 0x79: access_register8_high(0x78); gbc_sound_tone_control_low(3, 0x78); break; // Sound 4 control frequency case 0x7C: access_register8_low(0x7C); gbc_sound_noise_control(); break; case 0x7D: access_register8_high(0x7C); gbc_sound_noise_control(); break; // Sound control L case 0x80: access_register8_low(0x80); gbc_trigger_sound(); break; case 0x81: access_register8_high(0x80); gbc_trigger_sound(); break; // Sound control H case 0x82: access_register8_low(0x82); trigger_sound(); break; case 0x83: access_register8_high(0x82); trigger_sound(); break; // Sound control X case 0x84: sound_on(); break; // Sound wave RAM case 0x90 ... 0x9F: gbc_sound_wave_update = 1;
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