📄 x86_stub.s
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# gameplaySP## Copyright (C) 2006 Exophase <exophase@gmail.com>## This program is free software; you can redistribute it and/or# modify it under the terms of the GNU General Public License as# published by the Free Software Foundation; either version 2 of# the License, or (at your option) any later version.## This program is distributed in the hope that it will be useful,# but WITHOUT ANY WARRANTY; without even the implied warranty of# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU# General Public License for more details.## You should have received a copy of the GNU General Public License# along with this program; if not, write to the Free Software# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.align 4.global _x86_update_gba.global _x86_indirect_branch_arm.global _x86_indirect_branch_thumb.global _x86_indirect_branch_dual.global _execute_store_u8.global _execute_store_u16.global _execute_store_u32.global _execute_store_cpsr.global _execute_arm_translate.global _step_debug_x86.global _memory_map_read.global _memory_map_write.global _reg.global _oam_update.global _iwram.global _ewram.global _vram.global _oam_ram.global _bios_rom.global _io_registers.extern _spsr.equ REG_SP, (13 * 4).equ REG_LR, (14 * 4).equ REG_PC, (15 * 4).equ REG_N_FLAG, (16 * 4).equ REG_Z_FLAG, (17 * 4).equ REG_C_FLAG, (18 * 4).equ REG_V_FLAG, (19 * 4).equ REG_CPSR, (20 * 4).equ REG_SAVE, (21 * 4).equ REG_SAVE2, (22 * 4).equ REG_SAVE3, (23 * 4).equ CPU_MODE, (29 * 4).equ CPU_HALT_STATE, (30 * 4).equ CHANGED_PC_STATUS, (31 * 4)# destroys ecx and edx.macro collapse_flag offset, shift mov _reg + \offset, %ecx shl $\shift, %ecx or %ecx, %edx.endm.macro collapse_flags xor %edx, %edx collapse_flag REG_N_FLAG, 31 collapse_flag REG_Z_FLAG, 30 collapse_flag REG_C_FLAG, 29 collapse_flag REG_V_FLAG, 28 mov REG_CPSR(%ebx), %ecx and $0xFF, %ecx or %ecx, %edx mov %edx, REG_CPSR(%ebx).endm.macro extract_flag shift, offset mov REG_CPSR(%ebx), %edx shr $\shift, %edx and $0x01, %edx mov %edx, _reg + \offset.endm.macro extract_flags extract_flag 31, REG_N_FLAG extract_flag 30, REG_Z_FLAG extract_flag 29, REG_C_FLAG extract_flag 28, REG_V_FLAG.endm# Process a hardware event. Since an interrupt might be# raised we have to check if the PC has changed.# eax: current addressst: .asciz "u\n"_x86_update_gba: mov %eax, REG_PC(%ebx) # current PC = eax collapse_flags # update cpsr, trashes ecx and edx call _update_gba # process the next event mov %eax, %edi # edi = new cycle count # did the PC change? cmpl $1, CHANGED_PC_STATUS(%ebx) je lookup_pc ret # if not, go back to caller# Perform this on an indirect branch that will definitely go to# ARM code, IE anything that changes the PC in ARM mode except# for BX and data processing to PC with the S bit set.# eax: GBA address to branch to# edi: Cycle counter_x86_indirect_branch_arm: call _block_lookup_address_arm jmp *%eax# For indirect branches that'll definitely go to Thumb. In# Thumb mode any indirect branches except for BX._x86_indirect_branch_thumb: call _block_lookup_address_thumb jmp *%eax# For indirect branches that can go to either Thumb or ARM,# mainly BX (also data processing to PC with S bit set, be# sure to adjust the target with a 1 in the lowest bit for this)_x86_indirect_branch_dual: call _block_lookup_address_dual jmp *%eax# General ext memory routinesext_store_ignore: ret # ignore these writeswrite_epilogue: cmp $0, %eax # 0 return means nothing happened jz no_alert # if so we can leave collapse_flags # make sure flags are good for function call cmp $2, %eax # see if it was an SMC trigger je smc_writealert_loop: call _update_gba # process the next event # see if the halt status has changed mov CPU_HALT_STATE(%ebx), %edx cmp $0, %edx # 0 means it has jnz alert_loop # if not go again mov %eax, %edi # edi = new cycle count jmp lookup_pc # pc has definitely changedno_alert: retext_store_eeprom: jmp _write_eeprom # perform eeprom write# 8bit ext memory routinesext_store_io8: and $0x3FF, %eax # wrap around address and $0xFF, %edx call _write_io_register8 # perform 8bit I/O register write jmp write_epilogue # see if it requires any system updateext_store_palette8: and $0x3FE, %eax # wrap around address and align to 16bits jmp ext_store_palette16b # perform 16bit palette writeext_store_vram8: and $0x1FFFE, %eax # wrap around address and align to 16bits mov %dl, %dh # copy lower 8bits of value into full 16bits cmp $0x18000, %eax # see if address is in upper region jb ext_store_vram8b sub $0x8000, %eax # if so wrap downext_store_vram8b: mov %dx, _vram(%eax) # perform 16bit store retext_store_oam8: movl $1, _oam_update # flag OAM update and $0x3FE, %eax # wrap around address and align to 16bits mov %dl, %dh # copy lower 8bits of value into full 16bits mov %dx, _oam_ram(%eax) # perform 16bit store retext_store_backup: and $0xFF, %edx # make value 8bit and $0xFFFF, %eax # mask address jmp _write_backup # perform backup writeext_store_u8_jtable: .long ext_store_ignore # 0x00 BIOS, ignore .long ext_store_ignore # 0x01 invalid, ignore .long ext_store_ignore # 0x02 EWRAM, should have been hit already .long ext_store_ignore # 0x03 IWRAM, should have been hit already .long ext_store_io8 # 0x04 I/O registers .long ext_store_palette8 # 0x05 Palette RAM .long ext_store_vram8 # 0x06 VRAM .long ext_store_oam8 # 0x07 OAM RAM .long ext_store_ignore # 0x08 gamepak (no RTC accepted in 8bit) .long ext_store_ignore # 0x09 gamepak, ignore .long ext_store_ignore # 0x0A gamepak, ignore .long ext_store_ignore # 0x0B gamepak, ignore .long ext_store_ignore # 0x0C gamepak, ignore .long ext_store_eeprom # 0x0D EEPROM (possibly) .long ext_store_backup # 0x0E Flash ROM/SRAMext_store_u8: mov %eax, %ecx # ecx = address shr $24, %ecx # ecx = address >> 24 cmp $15, %ecx ja ext_store_ignore # ecx = ext_store_u8_jtable[address >> 24] mov ext_store_u8_jtable(, %ecx, 4), %ecx jmp *%ecx # jump to table index# eax: address to write to# edx: value to write# ecx: current pc_execute_store_u8: mov %ecx, REG_PC(%ebx) # write out the PC mov %eax, %ecx # ecx = address test $0xF0000000, %ecx # check address range
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