mips_stub.s

psp上的GBA模拟器

  region_check 2, \patch_handler
  translate_region_ewram_core 0x7FFF
.endm

.macro translate_region_ewram_load_align align_bits, alignment, patch_handler
  region_check_align 2, \align_bits, \alignment, \patch_handler
  translate_region_ewram_core 0x7FFF
.endm

.macro translate_region_ewram_load_align16 align_bits, alignment, patch_handler
  region_check_align 2, \align_bits, \alignment, \patch_handler
  translate_region_ewram_core 0x7FFE
.endm

.macro translate_region_ewram_load_align32 align_bits, alignment, patch_handler
  region_check_align 2, \align_bits, \alignment, \patch_handler
  translate_region_ewram_core 0x7FFC
.endm

.macro translate_region_ewram_store_align16 patch_handler
  region_check 2, \patch_handler
  translate_region_ewram_core 0x7FFE
.endm

.macro translate_region_ewram_store_align32 patch_handler
  region_check 2, \patch_handler
  translate_region_ewram_core 0x7FFC
.endm


.macro translate_region_vram_core
  addiu $2, $2, -3                # see if it's 3
  ext $4, $4, 0, 17               # generate 17bit offset
  bne $2, $0, 1f
  lui $1, %hi(vram)               # start loading vram address (delay)

  addiu $4, $4, -0x8000           # move address into VRAM region

1:
  addu $2, $1, $4                 # $2 = (hi)vram + address
.endm

.macro translate_region_vram patch_handler
  region_check 6, \patch_handler
  ext $2, $4, 15, 2               # $2 = bits 15 and 16 of address (delay)
  translate_region_vram_core
.endm

.macro translate_region_vram_load_align align_bits, alignment, patch_handler
  region_check_align 6, \align_bits, \alignment, \patch_handler
  ext $2, $4, 15, 2               # $2 = bits 15 and 16 of address (delay)
  translate_region_vram_core
.endm

.macro translate_region_vram_load_align16 align_bits, alignment, patch_handler
  region_check_align 6, \align_bits, \alignment, \patch_handler
  ext $2, $4, 15, 2               # $2 = bits 15 and 16 of address (delay)
  ins $4, $0, 0, 1                # mask out lower bit of address
  translate_region_vram_core
.endm

.macro translate_region_vram_load_align32 align_bits, alignment, patch_handler
  region_check_align 6, \align_bits, \alignment, \patch_handler
  ext $2, $4, 15, 2               # $2 = bits 15 and 16 of address (delay)
  ins $4, $0, 0, 2                # mask out lower two bits of address
  translate_region_vram_core
.endm

.macro translate_region_vram_store_align16 patch_handler
  region_check 6, \patch_handler
  ext $2, $4, 15, 2               # $2 = bits 15 and 16 of address (delay)
  ins $4, $0, 0, 1                # mask out lower bit of address
  translate_region_vram_core
.endm

.macro translate_region_vram_store_align32 patch_handler
  region_check 6, \patch_handler
  ext $2, $4, 15, 2               # $2 = bits 15 and 16 of address (delay)
  ins $4, $0, 0, 2                # mask out lower two bits of address
  translate_region_vram_core
.endm



.macro translate_region_gamepak_core mask
  srl $2, $4, 15                  # $2 = page number of address (delay)
  sll $2, $2, 2                   # adjust to word index
  addu $2, $2, $16                # $2 = memory_map_read[address >> 15]
  lw $2, -32768($2)
  bne $2, $0, 1f                  # if it's non-NULL continue
  andi $1, $4, \mask              # $1 = low 15bits of address (delay slot)

  sw $ra, REG_SAVE2($16)          # save return address

  save_registers                  # save the registers
  ext $4, $4, 15, 10              # $4 = (address >> 15) & 0x3FF

  jal load_gamepak_page           # get page in $2
  sw $1, REG_SAVE($16)            # save offset (delay)
  lw $1, REG_SAVE($16)            # restore offset (delay)

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE2($16)          # restore return address

1:
  addu $2, $2, $1                 # add the memory map offset
.endm

.macro translate_region_gamepak region, patch_handler
  region_check \region, \patch_handler
  translate_region_gamepak_core 0x7FFF
.endm

.macro translate_region_gamepak_align region, a_b, alignment, patch_handler
  region_check_align \region, \a_b, \alignment, \patch_handler
  translate_region_gamepak_core 0x7FFF
.endm

.macro translate_region_gamepak_align16 region, a_b, alignment, patch_handler
  region_check_align \region, \a_b, \alignment, \patch_handler
  translate_region_gamepak_core 0x7FFE
.endm

.macro translate_region_gamepak_align32 region, a_b, alignment, patch_handler
  region_check_align \region, \a_b, \alignment, \patch_handler
  translate_region_gamepak_core 0x7FFC
.endm


.macro translate_region_gamepak_a region, patch_handler
  region_check \region, \patch_handler
  srl $2, $4, 15                  # $2 = page number of address (delay)
  sll $2, $2, 2                   # adjust to word index
  addu $2, $2, $16                # $2 = memory_map_read[address >> 15]
  lw $2, -32768($2)
  bne $2, $0, 1f                  # if it's non-NULL continue
  andi $1, $4, 0x7FFF             # $1 = low 15bits of address (delay slot)

  sw $ra, REG_SAVE2($16)          # save return address
  sw $6, REG_SAVE3($16)           # save a2

  save_registers                  # save the registers
  ext $4, $4, 15, 10              # $4 = (address >> 15) & 0x3FF

  jal load_gamepak_page           # get page in $2
  sw $1, REG_SAVE($16)            # save offset (delay)
  lw $1, REG_SAVE($16)            # restore offset (delay)

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE2($16)          # restore return address
  lw $6, REG_SAVE3($16)           # restore a2

1:
  addu $2, $2, $1                 # add the memory map offset
.endm


.macro eeprom_load_a patch_handler
  region_check 0xD, \patch_handler

  sw $ra, REG_SAVE($16)           # save the return address (delay)
  sw $6, REG_SAVE2($16)           # save a2

  save_registers                  # save the registers

  jal read_eeprom                 # get eeprom value in $2
  nop

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
  lw $6, REG_SAVE2($16)           # restore a2
.endm


.macro eeprom_load_core
  sw $ra, REG_SAVE($16)           # save the return address (delay)

  save_registers                  # save the registers

  jal read_eeprom                 # get eeprom value in $2
  nop

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
  nop
.endm

.macro eeprom_load patch_handler
  region_check 0xD, \patch_handler
  eeprom_load_core
.endm

.macro eeprom_load_align align_bits, alignment, patch_handler
  region_check_align 0xD, \align_bits, \alignment, \patch_handler
  eeprom_load_core
.endm

.macro eeprom_load_align16 align_bits, alignment, patch_handler
  eeprom_load_align \align_bits, \alignment, \patch_handler
.endm

.macro eeprom_load_align32 align_bits, alignment, patch_handler
  eeprom_load_align \align_bits, \alignment, \patch_handler
.endm


.macro backup_load_core
  save_registers                  # save the registers

  jal read_backup                 # get backup value in $2
  ext $4, $4, 0, 16               # address &= 0xFFFF

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
.endm

.macro backup_load_a patch_handler
  region_check 0xE, \patch_handler
  sw $ra, REG_SAVE($16)           # save return address (delay)
  sw $6, REG_SAVE2($16)           # save a2

  save_registers                  # save the registers

  jal read_backup                 # get backup value in $2
  ext $4, $4, 0, 16               # address &= 0xFFFF

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
  lw $6, REG_SAVE2($16)           # restore a2
.endm


.macro backup_load patch_handler
  region_check 0xE, \patch_handler
  sw $ra, REG_SAVE($16)           # save the return address (delay)
  backup_load_core
.endm

.macro backup_load_align align_bits, alignment, patch_handler
  region_check_align 0xE, \align_bits, \alignment, \patch_handler
  sw $ra, REG_SAVE($16)           # save the return address (delay)
  backup_load_core
.endm

.macro backup_load_align16 align_bits, alignment, patch_handler
  region_check_align 0xE, \align_bits, \alignment, \patch_handler
  sw $ra, REG_SAVE($16)           # save the return address (delay)
  ins $4, $0, 0, 1                # mask out lower bit
  backup_load_core
.endm

.macro backup_load_align32 align_bits, alignment, patch_handler
  region_check_align 0xE, \align_bits, \alignment, \patch_handler
  sw $ra, REG_SAVE($16)           # save the return address (delay)
  ins $4, $0, 0, 2                # mask out lower two bits
  backup_load_core
.endm


.macro open_load8_core
  lw $2, REG_CPSR($16)            # $2 = CPSR (delay)
  andi $2, $2, 0x20               # test T bit
  beq $2, $0, 1f                  # branch if ARM mode
  andi $4, $4, 0x03               # isolate lower 3bits from address (delay)

  andi $4, $4, 0x01               # in Thumb mode, isolate one more bit

1:
  sw $ra, REG_SAVE($16)           # save the return address (delay)
  save_registers                  # save the registers

  jal read_memory8                # get instruction at PC
  addu $4, $5, $4                 # a0 = PC + low bits of address

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
.endm

.macro open_load8 patch_handler
  region_check_open \patch_handler
  open_load8_core
.endm



.macro open_load16_core
  lw $2, REG_CPSR($16)            # $2 = CPSR (delay)
  andi $2, $2, 0x20               # test T bit
  beq $2, $0, 1f                  # branch if ARM mode
  andi $4, $4, 0x02               # isolate bit 1 from address (delay)

  addu $4, $0, $0                 # zero out address bit

1:
  sw $ra, REG_SAVE($16)           # save the return address (delay)
  save_registers                  # save the registers

  jal read_memory16               # get instruction at PC
  addu $4, $5, $4                 # a0 = PC + low bits of address

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
.endm

.macro open_load16_align align_bits, alignment, patch_handler
  region_check_open_align \align_bits, \alignment, \patch_handler
  open_load16_core
.endm

.macro open_load16_align16 align_bits, alignment, patch_handler
  open_load16_align \align_bits, \alignment, \patch_handler
.endm



.macro open_load32_core
  lw $2, REG_CPSR($16)            # $2 = CPSR (delay)
  andi $2, $2, 0x20               # test T bit

  save_registers                  # save the registers

  beq $2, $0, 1f                  # branch if ARM mode
  sw $ra, REG_SAVE($16)           # save the return address (delay)

  jal read_memory16               # get instruction at PC
  addu $4, $5, $0                 # a0 = PC

  j 2f
  ins $2, $2, 16, 16              # result = (result << 16) | result (delay)

1:
  jal read_memory32               # get instruction at PC
  addu $4, $5, $4                 # a0 = PC

2:                                # join point
  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
.endm

.macro open_load32_a patch_handler
  region_check_open \patch_handler

  lw $2, REG_CPSR($16)            # $2 = CPSR (delay)
  andi $2, $2, 0x20               # test T bit

  save_registers                  # save the registers
  sw $6, REG_SAVE2($16)           # save a2

  beq $2, $0, 1f                  # branch if ARM mode
  sw $ra, REG_SAVE($16)           # save the return address (delay)

  jal read_memory16               # get instruction at PC
  addu $4, $5, $0                 # a0 = PC

  j 2f
  ins $2, $2, 16, 16              # result = (result << 16) | result (delay)

1:
  jal read_memory32               # get instruction at PC
  addu $4, $5, $4                 # a0 = PC

2:
  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
  lw $6, REG_SAVE2($16)           # restore a2 (delay)
.endm

.macro open_load32_align align_bits, alignment, patch_handler
  region_check_open_align \align_bits, \alignment, \patch_handler
  open_load32_core
.endm

.macro open_load32_align32 align_bits, alignment, patch_handler
  open_load32_align \align_bits, \alignment, \patch_handler
.endm


.macro store_function function, region, patch_handler, mask
  region_check \region, \patch_handler
  sw $ra, REG_SAVE($16)           # save the return address (delay)

  save_registers                  # save the registers

  jal \function                   # store value out
  andi $4, $4, \mask              # mask address

  restore_registers               # restore the other registers

  lw $ra, REG_SAVE($16)           # restore return address
  jr $ra                          # return
  nop
.endm


.macro store_function_a function, region, patch_handler, mask
  region_check \region, \patch_handler
  sw $ra, REG_SAVE($16)           # save the return address (delay)