ccc.vhd

来自「运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
entity ccc is
port(clk:in std_logic;
q500,qlk:out std_logic);
end ccc;
architecture ccc_arc of ccc is
signal x:std_logic;
begin
process(clk)
variable cnt:integer range 0 to 4999;
begin
if clk'event and clk='1'then
if cnt<1999 then
cnt:=cnt+1;
else
cnt:=0;
x<=not x;
end if;
end if;
qlk<=x;
end process;
process(x)
variable y:std_logic;
begin
if x'event and x='1' then
y:=not y;
end if;
q500<=y;
end process;
end ccc_arc;