clock.map.summary

运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!

Flow Status : Successful - Sun Nov 28 10:30:00 2004
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : FLEX10K
Device : EPF10K10TC144-4
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 137
Total pins : 15
Total memory bits : 0