sel.vhd

来自「运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel is
port (clk:in std_logic;
q:out std_logic_vector(2 downto 0));
end sel;
architecture sel_arc of sel is
begin
process(clk)
variable cnt:std_logic_vector(2 downto 0);
begin
if clk'event and clk='1' then
cnt:=cnt+1;
end if;
q<=cnt;
end process;
end sel_arc;