clock.tan.rpt

来自「运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用」· RPT 代码 · 共 260 行 · 第 1/5 页

; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                  ; To                                                                     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------------------------+------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 3.700 ns                         ; sb                                                                    ; hour:inst19|lpm_counter:cnt0_rtl_3|alt_counter_f10ke:wysi_counter|q[3] ;            ; sa       ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 57.200 ns                        ; hour:inst19|cnt1[2]                                                   ; t[6]                                                                   ; clk4m      ;          ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 15.200 ns                        ; sb                                                                    ; sound                                                                  ;            ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 24.000 ns                        ; sc                                                                    ; mian:inst1|co                                                          ;            ; clk4m    ; 0            ;
; Clock Setup: 'clk4m'         ; N/A                                      ; None          ; 25.84 MHz ( period = 38.700 ns ) ; mina:inst8|lpm_counter:cnt1_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; sst:inst4|q500                                                         ; clk4m      ; clk4m    ; 0            ;
; Clock Setup: 'sa'            ; N/A                                      ; None          ; 42.19 MHz ( period = 23.700 ns ) ; mian:inst1|lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] ; mian:inst1|lpm_counter:cnt1_rtl_2|alt_counter_f10ke:wysi_counter|q[0]  ; sa         ; sa       ; 0            ;
; Clock Hold: 'sa'             ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; mian:inst1|cnt0[0]                                                    ; mian:inst1|cnt0[0]                                                     ; sa         ; sa       ; 69           ;
; Clock Hold: 'clk4m'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; mina:inst8|cnt0[0]                                                    ; mina:inst8|cnt0[0]                                                     ; clk4m      ; clk4m    ; 24           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                       ;                                                                        ;            ;          ; 93           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------------------------+------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10TC144-4    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk4m           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sa              ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+