fen10.vhd

来自「运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
entity fen10 is
port(clk:in std_logic;
q:out std_logic);
end fen10;
architecture fen_arc of fen10 is
begin
process(clk)
variable cnt:integer range 0 to 9;
begin
if clk'event and clk='1'then
if cnt<9 then
cnt:=cnt+1;
q<='0';
else
cnt:=0;
q<='1';
end if;
end if;
end process;
end fen_arc;