📄 bbb.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
entity bbb is
port(sec1,sec0,min1,min0,h1,h0:out std_logic_vector(3 downto 0);
sel:out std_logic_vector(2 downto 0);
q:out std_logic_vector(3 downto 0));
end bbb;
architecture bbb_arc of bbb is
begin
process(sel)
begin
case sel is
when"000"=>q<=sec0;
when"001"=>q<=sec1;
when"011"=>q<=min0;
when"100"=>q<=min1;
when"110"=>q<=h0;
when"111"=>q<=h1;
when others=>q<="1111";
end case;
end process;
end bbb_arc;
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