hour.vhd

运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(en,clk:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end hour;
architecture hour_arc of hour is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
 begin
if clk'event and clk='1'then
if en='1'then
if cnt1="0010" and cnt0="0011"then
cnt0:="0000";
cnt1:="0000";
elsif cnt0<"1001"then
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;
end process;
end hour_arc;