disp.vhd.bak

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library ieee;
use ieee.std_logic_1164.all;
entity disp is
port(d:in std_logic_vector(3downto 0);
q:out std_logic_vector(6 downto 0));
end disp;
architecture disp_arc of disp is
begin
process(d)
begin
case d is
when"0000"=>q<="0111111";
when"0001"=>q<="0000110";
when"0010"=>q<="1011011";
when"0011"=>q<="1001111";
when"0100"=>q<="1100110";
when"0101"=>q<="1101101";
when"0110"=>q<="11111101";
when"0111"=>q<="0100111";
when"1000"=>q<="1111111";
when"1001"=>q<="1101111";
when others=>q<="0000000";
end case;
end process;
end disp_arc;