sst.vhd.bak

运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!

library ieee;
use ieee.std_logic_1164.all;
entity sst is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,qlk:out std_logic);
end sst;
architecture sst_arc of sst is
begin
process(clk)
begin
if clk'event clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0000" or s0="0010" or s0="0100" or s0="0110" or s0="1000" then
q500<='1';
else
q500<='0';
end if;
end if;
if m1="0000" and m0="0000" and s1="0000" and s0="0000" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sst_arc;