mina.vhd

运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mina is
port(en,clk:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end mina;
architecture min_arc of mina is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1'then
if en='1'then
if cnt1="0101" and cnt0="1000"then
co<='1';
cnt0:="1001";
elsif cnt0<"1001"then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101"then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;
end process;
end min_arc;