clock.map.rpt

运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!

; lpm_counter.tdf                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; alt_counter_f10ke.tdf            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf   ;
; flex10ke_lcell.inc               ; yes             ; c:/altera/quartus42/libraries/megafunctions/flex10ke_lcell.inc      ;
; lpm_add_sub.tdf                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; c:/altera/quartus42/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf                      ; yes             ; c:/altera/quartus42/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 137     ;
; Total combinational functions     ; 130     ;
; Total 4-input functions           ; 56      ;
; Total 3-input functions           ; 15      ;
; Total 2-input functions           ; 30      ;
; Total 1-input functions           ; 29      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 60      ;
; Total logic cells in carry chains ; 41      ;
; I/O pins                          ; 15      ;
; Maximum fan-out node              ; inst3   ;
; Maximum fan-out                   ; 17      ;
; Total fan-out                     ; 491     ;
; Average fan-out                   ; 3.23    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sun Nov 28 10:29:56 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file ../../szz/clock.bdf
    Info: Found entity 1: clock
Info: Using design file sst.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sst-sst_arc
    Info: Found entity 1: sst
Info: Using design file mina.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: mina-min_arc
    Info: Found entity 1: mina
Info: Using design file mian.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: mian-mian_arc
    Info: Found entity 1: mian
Info: Using design file fen10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fen10-fen_arc
    Info: Found entity 1: fen10
Info: Using design file ccc.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ccc-ccc_arc
    Info: Found entity 1: ccc
Warning: VHDL Process Statement warning at ccc.vhd(21): signal "x" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Using design file disp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: disp-disp_arc
    Info: Found entity 1: disp
Info: Using design file bbb.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bbb-bbb_arc
    Info: Found entity 1: bbb
Warning: VHDL Process Statement warning at bbb.vhd(13): signal "sec0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bbb.vhd(14): signal "sec1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bbb.vhd(15): signal "min0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bbb.vhd(16): signal "min1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bbb.vhd(17): signal "h0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bbb.vhd(18): signal "h1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bbb.vhd(10): signal or variable "q" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "q" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file hour.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: hour-hour_arc
    Info: Found entity 1: hour
Info: Using design file sel.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sel-sel_arc
    Info: Found entity 1: sel
Info: Inferred 7 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: "ccc:inst22|cnt[0]~13"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "mina:inst8|cnt1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "mian:inst1|cnt1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour:inst19|cnt0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "fen10:inst28|cnt[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "fen10:inst25|cnt[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "fen10:inst24|cnt[0]~4"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "sel:inst23|cnt[0]" merged to single register "ccc:inst22|q500"
Info: Implemented 152 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 11 output pins
    Info: Implemented 137 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Sun Nov 28 10:30:00 2004
    Info: Elapsed time: 00:00:04