📄 clock.map.rpt
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; EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ; <None> ;
; EDA_BOARD_DESIGN_SYMBOL_TOOL ; <None> ;
; EDA_BOARD_DESIGN_TIMING_TOOL ; <None> ;
; ENABLE_ASMI_FOR_FLASH_LOADER ; Off ;
; ENABLE_CLOCK_LATENCY ; Off ;
; ENABLE_HOLD_BACK_OFF ; On ;
; ENABLE_OCT_DONE ; Off ;
; ENABLE_REDUCED_MEMORY_MODE ; Off ;
; EQC_AUTO_BREAK_CONE ; On ;
; EQC_AUTO_COMP_LOOP_CUT ; On ;
; EQC_AUTO_INVERSION ; On ;
; EQC_AUTO_PORTSWAP ; On ;
; EQC_AUTO_TERMINATE ; On ;
; EQC_BBOX_MERGE ; On ;
; EQC_CONSTANT_DFF_DETECTION ; On ;
; EQC_DETECT_DONT_CARES ; On ;
; EQC_DFF_SS_EMULATION ; On ;
; EQC_DUPLICATE_DFF_DETECTION ; On ;
; EQC_LVDS_MERGE ; On ;
; EQC_MAC_REGISTER_UNPACK ; On ;
; EQC_PARAMETER_CHECK ; On ;
; EQC_POWER_UP_COMPARE ; Off ;
; EQC_RAM_REGISTER_UNPACK ; On ;
; EQC_RAM_UNMERGING ; On ;
; EQC_RENAMING_RULES ; On ;
; EQC_SET_PARTITION_BB_TO_VCC_GND ; On ;
; EQC_SHOW_ALL_MAPPED_POINTS ; Off ;
; EQC_STRUCTURE_MATCHING ; On ;
; EQC_SUB_CONE_REPORT ; Off ;
; FIT_ATTEMPTS_TO_SKIP ; 0.0 ;
; FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ; Automatically ;
; FLOW_ENABLE_HCII_COMPARE ; Off ;
; FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ; Off ;
; FLOW_ENABLE_RTL_VIEWER ; Off ;
; FLOW_ENABLE_TIMING_CONSTRAINT_CHECK ; Off ;
; FLOW_HARDCOPY_DESIGN_READINESS_CHECK ; On ;
; FORCE_CONFIGURATION_VCCIO ; Off ;
; FORCE_SYNCH_CLEAR ; Off ;
; GENERATE_GXB_RECONFIG_MIF ; Off ;
; GENERATE_GXB_RECONFIG_MIF_WITH_PLL ; Off ;
; HARDCOPYII_POWER_ON_EXTRA_DELAY ; Off ;
; HCII_OUTPUT_DIR ; hc_output ;
; HDL_MESSAGE_LEVEL ; Level2 ;
; IGNORE_MAX_FANOUT_ASSIGNMENTS ; Off ;
; IGNORE_MODE_FOR_MERGE ; Off ;
; IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF ; Off ;
; IGNORE_VERILOG_INITIAL_CONSTRUCTS ; Off ;
; INCREMENTAL_COMPILATION ; OFF ;
; INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE ; POST_FIT ;
; MAX_BALANCING_DSP_BLOCKS ; -1 (Unlimited) ;
; MAX_RAM_BLOCKS_M4K ; -1 (Unlimited) ;
; MAX_RAM_BLOCKS_M512 ; -1 (Unlimited) ;
; MAX_RAM_BLOCKS_MRAM ; -1 (Unlimited) ;
; MIGRATION_CONSTRAIN_CORE_RESOURCES ; On ;
; NUM_PARALLEL_PROCESSORS ; 1 ;
; NUMBER_OF_REMOVED_REGISTERS_REPORTED ; 100 ;
; OPTIMIZE_POWER_DURING_FITTING ; Normal compilation ;
; OPTIMIZE_POWER_DURING_SYNTHESIS ; Normal compilation ;
; PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ; Off ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; Off ;
; PHYSICAL_SYNTHESIS_LOG_FILE ; Off ;
; PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ; Off ;
; POWER_BOARD_TEMPERATURE ; 25 ;
; POWER_REPORT_POWER_DISSIPATION ; ON ;
; POWER_USE_INPUT_FILES ; Off ;
; PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES ; 1.0 ;
; PROGRAMMABLE_POWER_TECHNOLOGY_SETTING ; Automatic ;
; PROJECT_USE_SIMPLIFIED_NAMES ; Off ;
; READ_OR_WRITE_IN_BYTE_ADDRESS ; Use global settings ;
; RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP ; As input tri-stated with weak pull-up ;
; RESERVE_DATA1_AFTER_CONFIGURATION ; As input tri-stated ;
; RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION ; Use as regular IO ;
; RESERVE_DCLK_AFTER_CONFIGURATION ; Use as programming pin ;
; RESERVE_FLASH_NCE_AFTER_CONFIGURATION ; As input tri-stated ;
; RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION ; Use as regular IO ;
; ROUTER_TIMING_OPTIMIZATION_LEVEL ; Normal ;
; RTLV_GROUP_COMB_LOGIC_IN_CLOUD ; Off ;
; RTLV_GROUP_RELATED_NODES ; On ;
; RTLV_REMOVE_FANOUT_FREE_REGISTERS ; On ;
; RTLV_SIMPLIFIED_LOGIC ; On ;
; RUN_FULL_COMPILE_ON_DEVICE_CHANGE ; On ;
; SAFE_STATE_MACHINE ; Off ;
; SAVE_INTERMEDIATE_FITTING_RESULTS ; Off ;
; SAVE_MIGRATION_INFO_DURING_COMPILATION ; Off ;
; SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED ; Off ;
; SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT ; On ;
; SIMULATION_BUS_CHANNEL_GROUPING ; Off ;
; SIMULATION_CELL_DELAY_MODEL_TYPE ; TRANSPORT ;
; SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL ; On ;
; SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE ; TRANSPORT ;
; SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL ; On ;
; SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL ; On ;
; SIMULATION_NETLIST_VIEWER ; Off ;
; SIMULATION_VDB_RESULT_FLUSH ; On ;
; SIMULATION_WITH_AUTO_GLITCH_FILTERING ; AUTO ;
; SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF ; OFF ;
; SIMULATOR_GENERATE_POWERPLAY_VCD_FILE ; Off ;
; SIMULATOR_PVT_TIMING_MODEL_TYPE ; AUTO ;
; SMART_RECOMPILE ; NORMAL ;
; STOP_AFTER_CONGESTION_MAP ; Off ;
; STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT ; Off ;
; STRATIXII_CONFIGURATION_DEVICE ; Auto ;
; STRATIXII_CONFIGURATION_SCHEME ; Passive Serial ;
; STRATIXII_MRAM_COMPATIBILITY ; ON ;
; STRATIXIII_CONFIGURATION_SCHEME ; Passive Serial ;
; STRATIXIII_UPDATE_MODE ; Standard ;
; SUPPRESS_REG_MINIMIZATION_MSG ; Off ;
; SYNTH_CLOCK_MUX_PROTECTION ; On ;
; TIMEQUEST_DO_REPORT_TIMING ; Off ;
; TREAT_BIDIR_AS_OUTPUT ; Off ;
; USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT ; Off ;
; USE_HIGH_SPEED_ADDER ; Auto ;
; VECTOR_COMPARE_TRIGGER_MODE ; INPUT_EDGE ;
; XSTL_INPUT_ALLOW_SE_BUFFER ; Off ;
+---------------------------------------------------------------------------+---------------------------------------+
+-----------+
; Hierarchy ;
+-----------+
clock
|-- mian:inst1
|-- lpm_counter:cnt1_rtl_2
|-- alt_counter_f10ke:wysi_counter
|-- sst:inst4
|-- mina:inst8
|-- lpm_counter:cnt1_rtl_1
|-- alt_counter_f10ke:wysi_counter
|-- bbb:inst17
|-- disp:inst18
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