clock.map.rpt

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Analysis & Synthesis report for clock
Sun Nov 28 10:30:00 2004
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Hierarchy
  6. User-Specified and Inferred Latches
  7. General Register Statistics
  8. WYSIWYG Cells
  9. Analysis & Synthesis Resource Utilization by Entity
 10. Analysis & Synthesis Equations
 11. Analysis & Synthesis Source Files Read
 12. Analysis & Synthesis Resource Usage Summary
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Nov 28 10:30:00 2004    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; clock                                    ;
; Top-level Entity Name       ; clock                                    ;
; Family                      ; FLEX10K                                  ;
; Total logic elements        ; 137                                      ;
; Total pins                  ; 15                                       ;
; Total memory bits           ; 0                                        ;
+-----------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                          ;
+------------------------------------------------------+-----------------+---------------+
; Option                                               ; Setting         ; Default Value ;
+------------------------------------------------------+-----------------+---------------+
; Device                                               ; EPF10K10TC144-4 ;               ;
; Family name                                          ; FLEX10K         ; Stratix       ;
; Use smart compilation                                ; Normal          ; Normal        ;
; Create Debugging Nodes for IP Cores                  ; off             ; off           ;
; Preserve fewer node names                            ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation            ; Off             ; Off           ;
; Verilog Version                                      ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                         ; VHDL93          ; VHDL93        ;
; Top-level entity name                                ; clock           ; clock         ;
; State Machine Processing                             ; Auto            ; Auto          ;
; Extract Verilog State Machines                       ; On              ; On            ;
; Extract VHDL State Machines                          ; On              ; On            ;
; NOT Gate Push-Back                                   ; On              ; On            ;
; Power-Up Don't Care                                  ; On              ; On            ;
; Remove Redundant Logic Cells                         ; Off             ; Off           ;
; Remove Duplicate Registers                           ; On              ; On            ;
; Ignore CARRY Buffers                                 ; Off             ; Off           ;
; Ignore CASCADE Buffers                               ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                            ; Off             ; Off           ;
; Ignore LCELL Buffers                                 ; Off             ; Off           ;
; Ignore SOFT Buffers                                  ; On              ; On            ;
; Limit AHDL Integers to 32 Bits                       ; Off             ; Off           ;
; Auto Implement in ROM                                ; Off             ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area            ; Area          ;
; Carry Chain Length -- FLEX 10K                       ; 32              ; 32            ;
; Cascade Chain Length                                 ; 2               ; 2             ;
; Auto Carry Chains                                    ; On              ; On            ;
; Auto Open-Drain Pins                                 ; On              ; On            ;
; Remove Duplicate Logic                               ; On              ; On            ;
; Auto ROM Replacement                                 ; On              ; On            ;
; Auto RAM Replacement                                 ; On              ; On            ;
; Auto Clock Enable Replacement                        ; On              ; On            ;
; Auto Resource Sharing                                ; Off             ; Off           ;
; Allow Any RAM Size For Recognition                   ; Off             ; Off           ;
; Allow Any ROM Size For Recognition                   ; Off             ; Off           ;
+------------------------------------------------------+-----------------+---------------+


+-------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings                                                                   ;
+---------------------------------------------------------------------------+---------------------------------------+
; Name                                                                      ; Setting                               ;
+---------------------------------------------------------------------------+---------------------------------------+
; ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS                                   ; On                                    ;
; ADV_NETLIST_OPT_METASTABLE_REGS                                           ; 2                                     ;
; AUTO_EXPORT_INCREMENTAL_COMPILATION                                       ; Off                                   ;
; AUTO_RAM_TO_LCELL_CONVERSION                                              ; Off                                   ;
; BLOCK_DESIGN_NAMING                                                       ; Auto                                  ;
; BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES                    ; Care                                  ;
; BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS                         ; Auto                                  ;
; BLOCK_RAM_TO_MLAB_CELL_CONVERSION                                         ; On                                    ;
; CLK_RULE_CLKNET_CLKSPINES_THRESHOLD                                       ; 25                                    ;
; CONFIGURATION_VCCIO_LEVEL                                                 ; Auto                                  ;
; CYCLONEII_M4K_COMPATIBILITY                                               ; On                                    ;
; CYCLONEIII_CONFIGURATION_DEVICE                                           ; Auto                                  ;
; CYCLONEIII_CONFIGURATION_SCHEME                                           ; Active Serial                         ;
; DO_COMBINED_ANALYSIS                                                      ; Off                                   ;
; DRC_DEADLOCK_STATE_LIMIT                                                  ; 2                                     ;
; DRC_DETAIL_MESSAGE_LIMIT                                                  ; 10                                    ;
; DRC_GATED_CLOCK_FEED                                                      ; 30                                    ;
; DRC_VIOLATION_MESSAGE_LIMIT                                               ; 30                                    ;