📄 m16_twi_24cx.lst
字号:
(0050) txd_buf[i]=r_buf[i];
01BD EA80 LDI R24,0xA0
01BE E090 LDI R25,0
01BF 81EA LDD R30,Y+2
01C0 81FB LDD R31,Y+3
01C1 0FE8 ADD R30,R24
01C2 1FF9 ADC R31,R25
01C3 8020 LDD R2,Z+0
01C4 EE80 LDI R24,0xE0
01C5 E090 LDI R25,0
01C6 81EA LDD R30,Y+2
01C7 81FB LDD R31,Y+3
01C8 0FE8 ADD R30,R24
01C9 1FF9 ADC R31,R25
01CA 8220 STD Z+0,R2
01CB 818A LDD R24,Y+2
01CC 819B LDD R25,Y+3
01CD 9601 ADIW R24,1
01CE 839B STD Y+3,R25
01CF 838A STD Y+2,R24
01D0 818A LDD R24,Y+2
01D1 819B LDD R25,Y+3
01D2 3480 CPI R24,0x40
01D3 E0E0 LDI R30,0
01D4 079E CPC R25,R30
01D5 F338 BCS 0x01BD
(0051)
(0052) txd_buf[69]=syserr;
01D6 90200126 LDS R2,syserr
01D8 92200125 STS 0x125,R2
(0053)
(0054) txdpo(txd_buf, 69);
01DA E425 LDI R18,0x45
01DB EE00 LDI R16,0xE0
01DC E010 LDI R17,0
01DD 940E020F CALL _txdpo
(0055)
(0056) while(1);
01DF CFFF RJMP 0x01DF
(0057) //----------------------------
(0058)
(0059) c=0;
01E0 2400 CLR R0
01E1 2411 CLR R1
01E2 821D STD Y+5,R1
01E3 820C STD Y+4,R0
01E4 9626 ADIW R28,6
01E5 9508 RET
(0060)
(0061)
(0062) }
(0063)
(0064)
(0065)
(0066) //-------------------------------------------------------------------------------------------------------------------------
(0067) //ICC-AVR application builder : 2005-11-9 22:09:34
(0068) // Target : M16
(0069) // Crystal: 8.0000Mhz
(0070)
(0071)
(0072) void port_init(void)
(0073) {
(0074) PORTA = 0xFF;
_port_init:
01E6 EF8F LDI R24,0xFF
01E7 BB8B OUT 0x1B,R24
(0075) DDRA = 0x00;
01E8 2422 CLR R2
01E9 BA2A OUT 0x1A,R2
(0076) PORTB = 0xFF;
01EA BB88 OUT 0x18,R24
(0077) DDRB = 0x00;
01EB BA27 OUT 0x17,R2
(0078) PORTC = 0xFF; //m103 output only
01EC BB85 OUT 0x15,R24
(0079) DDRC = 0x00;
01ED BA24 OUT 0x14,R2
(0080) PORTD = 0xFF;
01EE BB82 OUT 0x12,R24
(0081) DDRD = 0x00;
01EF BA21 OUT 0x11,R2
01F0 9508 RET
(0082) }
(0083)
(0084) //TWI initialize
(0085) // bit rate:100
(0086) void twi_init(void)
(0087) {
(0088) TWCR= 0X00; //disable twi
_twi_init:
01F1 2422 CLR R2
01F2 BE26 OUT 0x36,R2
(0089) TWBR= 0x64; //set bit rate
01F3 E684 LDI R24,0x64
01F4 B980 OUT 0x00,R24
(0090) TWSR= 0x00; //set prescale
01F5 B821 OUT 0x01,R2
(0091) TWAR= 0x00; //set slave address
01F6 B822 OUT 0x02,R2
(0092) TWCR= 0x04; //enable twi
01F7 E084 LDI R24,4
01F8 BF86 OUT 0x36,R24
01F9 9508 RET
(0093) }
(0094)
(0095) //UART0 initialize
(0096) // desired baud rate: 9600
(0097) // actual: baud rate:9615 (0.2%)
(0098) // char size: 8 bit
(0099) // parity: Disabled
(0100) void uart0_init(void)
(0101) {
(0102) UCSRB = 0x00; //disable while setting baud rate
_uart0_init:
01FA 2422 CLR R2
01FB B82A OUT 0x0A,R2
(0103) UCSRA = 0x00;
01FC B82B OUT 0x0B,R2
(0104) UCSRC = BIT(URSEL) | 0x06;
01FD E886 LDI R24,0x86
01FE BD80 OUT 0x20,R24
(0105) UBRRL = 0x33; //set baud rate lo
01FF E383 LDI R24,0x33
0200 B989 OUT 0x09,R24
(0106) UBRRH = 0x00; //set baud rate hi
0201 BC20 OUT 0x20,R2
(0107) UCSRB = 0x08;
0202 E088 LDI R24,0x8
0203 B98A OUT 0x0A,R24
0204 9508 RET
(0108) }
(0109)
(0110) //call this routine to initialize all peripherals
(0111) void setreg_m16(void)
(0112) {
(0113) //stop errant interrupts until set up
(0114) CLI(); //disable all interrupts
_setreg_m16:
0205 94F8 BCLR 7
(0115) port_init();
0206 DFDF RCALL _port_init
(0116) twi_init();
0207 DFE9 RCALL _twi_init
(0117) uart0_init();
0208 DFF1 RCALL _uart0_init
(0118)
(0119) MCUCR = 0x00;
0209 2422 CLR R2
020A BE25 OUT 0x35,R2
(0120) GICR = 0x00;
020B BE2B OUT 0x3B,R2
(0121) TIMSK = 0x00; //timer interrupt sources
020C BE29 OUT 0x39,R2
(0122) SEI(); //re-enable interrupts
020D 9478 BSET 7
020E 9508 RET
FILE: E:\avr\m16_twi_24x\Debug_com.C
(0001) #include<iom16v.h> //在此设定avr类MCU的头文件
(0002) #include<macros.h>
(0003) #include"xd.h"
(0004) #include"xdprj.h"
(0005)
(0006)
(0007)
(0008)
(0009)
(0010) //参数:1)为要发送数据的起始地址, 2)a为数据长度
(0011) void txdpo(uchar *txdbuf, uchar a)
(0012) {
(0013) for(;a>0;a--)
_txdpo:
a --> R18
txdbuf --> R16
020F C008 RJMP 0x0218
(0014) { UDR=*txdbuf;
0210 01F8 MOVW R30,R16
0211 8020 LDD R2,Z+0
0212 B82C OUT 0x0C,R2
(0015) txdbuf++;
0213 5F0F SUBI R16,0xFF
0214 4F1F SBCI R17,0xFF
(0016) while(!(UCSRA & BIT(UDRE)));
FILE: <library>
0215 9B5D SBIS 0x0B,5
0216 CFFE RJMP 0x0215
0217 952A DEC R18
0218 2422 CLR R2
0219 1622 CP R2,R18
021A F3A8 BCS 0x0210
021B 9508 RET
push_arg4:
021C 933A ST R19,-Y
021D 932A ST R18,-Y
push_arg2:
021E 931A ST R17,-Y
021F 930A ST R16,-Y
0220 9508 RET
empy16s:
0221 920A ST R0,-Y
0222 921A ST R1,-Y
0223 938A ST R24,-Y
0224 939A ST R25,-Y
0225 9F02 MUL R16,R18
0226 01C0 MOVW R24,R0
0227 9F12 MUL R17,R18
0228 0D90 ADD R25,R0
0229 9F03 MUL R16,R19
022A 0D90 ADD R25,R0
022B 018C MOVW R16,R24
022C 9199 LD R25,Y+
022D 9189 LD R24,Y+
022E 9019 LD R1,Y+
022F 9009 LD R0,Y+
0230 9508 RET
empy32u:
empy32s:
0231 940E0286 CALL long_prolog
0233 927F PUSH R7
0234 940E029F CALL tstzero1
0236 F139 BEQ 0x025E
0237 2477 CLR R7
0238 940E02A5 CALL tstzero2
023A F419 BNE 0x023E
023B 018C MOVW R16,R24
023C 019D MOVW R18,R26
023D C020 RJMP 0x025E
023E 9F08 MUL R16,R24
023F 2CB0 MOV R11,R0
0240 2CA1 MOV R10,R1
0241 9F28 MUL R18,R24
0242 2C90 MOV R9,R0
0243 2C81 MOV R8,R1
0244 9F18 MUL R17,R24
0245 0CA0 ADD R10,R0
0246 1C91 ADC R9,R1
0247 1C87 ADC R8,R7
0248 9F09 MUL R16,R25
0249 0CA0 ADD R10,R0
024A 1C91 ADC R9,R1
024B 1C87 ADC R8,R7
024C 9F19 MUL R17,R25
024D 0C90 ADD R9,R0
024E 1C81 ADC R8,R1
024F 9F0A MUL R16,R26
0250 0C90 ADD R9,R0
0251 1C81 ADC R8,R1
0252 9F38 MUL R19,R24
0253 0C80 ADD R8,R0
0254 9F29 MUL R18,R25
0255 0C80 ADD R8,R0
0256 9F1A MUL R17,R26
0257 0C80 ADD R8,R0
0258 9F0B MUL R16,R27
0259 0C80 ADD R8,R0
025A 2D0B MOV R16,R11
025B 2D1A MOV R17,R10
025C 2D29 MOV R18,R9
025D 2D38 MOV R19,R8
025E 907F POP R7
025F 940C0294 JMP long_epilog
pop_gset4:
0261 E0E8 LDI R30,0x8
0262 940C0273 JMP pop
pop_gset5:
0264 27EE CLR R30
0265 940C0273 JMP pop
push_gset5:
0267 92FA ST R15,-Y
0268 92EA ST R14,-Y
push_gset4:
0269 92DA ST R13,-Y
026A 92CA ST R12,-Y
push_gset3:
026B 92BA ST R11,-Y
026C 92AA ST R10,-Y
push_gset2:
026D 937A ST R23,-Y
026E 936A ST R22,-Y
push_gset1:
026F 935A ST R21,-Y
0270 934A ST R20,-Y
0271 9508 RET
pop_gset1:
0272 E0E1 LDI R30,1
pop:
0273 9149 LD R20,Y+
0274 9159 LD R21,Y+
0275 FDE0 SBRC R30,0
0276 9508 RET
0277 9169 LD R22,Y+
0278 9179 LD R23,Y+
0279 FDE1 SBRC R30,1
027A 9508 RET
027B 90A9 LD R10,Y+
027C 90B9 LD R11,Y+
027D FDE2 SBRC R30,2
027E 9508 RET
027F 90C9 LD R12,Y+
0280 90D9 LD R13,Y+
0281 FDE3 SBRC R30,3
0282 9508 RET
0283 90E9 LD R14,Y+
0284 90F9 LD R15,Y+
0285 9508 RET
long_prolog:
0286 928A ST R8,-Y
0287 929A ST R9,-Y
0288 92AA ST R10,-Y
0289 92BA ST R11,-Y
028A 93EA ST R30,-Y
028B 938A ST R24,-Y
028C 939A ST R25,-Y
028D 93AA ST R26,-Y
028E 93BA ST R27,-Y
028F 8589 LDD R24,Y+9
0290 859A LDD R25,Y+10
0291 85AB LDD R26,Y+11
0292 85BC LDD R27,Y+12
0293 9508 RET
long_epilog:
0294 91B9 LD R27,Y+
0295 91A9 LD R26,Y+
0296 9199 LD R25,Y+
0297 9189 LD R24,Y+
0298 91E9 LD R30,Y+
0299 90B9 LD R11,Y+
029A 90A9 LD R10,Y+
029B 9099 LD R9,Y+
029C 9089 LD R8,Y+
029D 9624 ADIW R28,4
029E 9508 RET
tstzero1:
029F 27EE CLR R30
02A0 2BE0 OR R30,R16
02A1 2BE1 OR R30,R17
02A2 2BE2 OR R30,R18
02A3 2BE3 OR R30,R19
02A4 9508 RET
tstzero2:
02A5 27EE CLR R30
02A6 2BE8 OR R30,R24
02A7 2BE9 OR R30,R25
02A8 2BEA OR R30,R26
02A9 2BEB OR R30,R27
02AA 9508 RET
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