📄 dai_test.c
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/*****************************************************************************
* dai_test.c: DAI test main C entry file for NXP
* LPC2xxx Family Microprocessors
*
* Copyright(C) 2006, NXP Semiconductor
* All rights reserved.
*
* History
* 2006.07.14 ver 1.00 Prelimnary version, first Release
*
******************************************************************************/
#include "LPC288x.h" /* LPC2xxx definitions */
#include "type.h"
#include "irq.h"
#include "target.h"
#include "ex_sdram.h"
static DWORD word_cnt;
static DWORD cnt;
volatile DWORD *rd_ptr;
volatile DWORD *wr_ptr;
void DAI_ISR(void)
{
DWORD status, data;
status = SAISTAT1;
if (status & 0x010)
{
if (word_cnt >= 0x100000)
{
wr_ptr = (DWORD *)SDRAM_BASE_ADDR;
word_cnt = 0;
}
data = LR32IN1;
*wr_ptr = data;
wr_ptr ++;
data = LR32IN1;
*wr_ptr = data;
wr_ptr ++;
data = LR32IN1;
*wr_ptr = data;
wr_ptr ++;
data = LR32IN1;
*wr_ptr = data;
wr_ptr ++;
word_cnt += 4;
SAISTAT1 = 0x3FF;
}
}
void DAO_ISR(void)
{
DWORD status, data;
status = SAOSTAT1;
if (status & 0x040)
{
if (word_cnt >= 0x100000)
{
rd_ptr = (DWORD *)SDRAM_BASE_ADDR;
word_cnt = 0;
}
data = *rd_ptr;
rd_ptr ++;
LR32OUT1 = data;
data = *rd_ptr;
rd_ptr ++;
LR32OUT1 = data;
data = *rd_ptr;
rd_ptr ++;
LR32OUT1 = data;
data = *rd_ptr;
rd_ptr ++;
LR32OUT1 = data;
word_cnt += 4;
SAOSTAT1 = 0x3FF;
}
}
void DADC_ISR(void)
{
DWORD status, data;
status = SAISTAT4;
if (status & 0x010)
{
status = DECSTAT;
if (status & 0x2)
{
return;
}
if (word_cnt < 0x100000)
{
data = LR32IN4;
*wr_ptr = data;
wr_ptr ++;
data = LR32IN4;
*wr_ptr = data;
wr_ptr ++;
data = LR32IN4;
*wr_ptr = data;
wr_ptr ++;
data = LR32IN4;
*wr_ptr = data;
wr_ptr ++;
word_cnt += 4;
SAISTAT4 = 0x3FF;
}
}
}
void DDAC_ISR(void)
{
DWORD status, data;
status = SAOSTAT2;
if (status & 0x040)
{
if (word_cnt >= 0x100000)
{
rd_ptr = (DWORD *)SDRAM_BASE_ADDR;
word_cnt = 0;
cnt += 1;
}
data = *rd_ptr;
rd_ptr ++;
LR32OUT2 = data;
data = *rd_ptr;
rd_ptr ++;
LR32OUT2 = data;
data = *rd_ptr;
rd_ptr ++;
LR32OUT2 = data;
data = *rd_ptr;
rd_ptr ++;
LR32OUT2 = data;
word_cnt += 4;
SAOSTAT2 = 0x3FF;
}
}
/*****************************************************************************
** Main Function main()
******************************************************************************/
int main (void)
{
DWORD status, config;
TargetResetInit();
/* initialize memory */
SDRAMInit();
wr_ptr = (DWORD *)SDRAM_BASE_ADDR;
word_cnt = 0;
cnt = 0;
/* initialize I2S */
SIOCR = 0xFF;
I2S_FMT = 0x11C;
/* initialize High Speed PLL */
HPMODE = 0x04;
HPFIN = 0x01;
HPNDEC = 131;
HPMDEC = 1408;
HPPDEC = 23;
HPSELR = 8;
HPSELI = 2;
HPSELP = 31;
HPMODE = 0x01;
status = HPSTAT;
while ((status & 1) == 0)
{
status = HPSTAT;
}
/* configurate Selection Stages */
DAIOFSR2 = 0x07;
DAIOSCR = 0x02;
DAIFSR2 = 0x03;
DAISCR = 0x02;
/* configurate Spreading Stages */
/* Disable Fractional Divider in the Base Control register. */
DAIOBCR = 0;
/* Clear RUN bit in FDCR, fractional divider 0 */
DAIOFDCR0 &= ~0x01;
/* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
MADD is 0x48(72), MSUB is 0xE8(232). where m = 0x60 and
n = 0x18. FDR is divided by 4. */
config = (((DAIOFDCR0_MSUB << 8) | DAIOFDCR0_MADD) << 3) | (0x1 << 2) | (0x1 << 1);
DAIOFDCR0 = config;
/* Clear Reset(FDRES) bit */
config &= ~0x2;
DAIOFDCR0 = config;
/* Set RUN bit(FDRUN). */
config |= 0x1;
DAIOFDCR0 = config;
/* Enable Select Register setting. ESR with 3 bit fields.
bit 0 ESR_EN is 1 causing spreading stage output clock under
the control of the fractional divider, which runs slower
than the selection stage clock. ESR_SEL, bits 3:1 is 0, FDR0 is
selected for DDAC ESR1. */
DDACESR1 = (0x0<<1) | (0x1<<0);
/* Clear RUN bit in FDCR, fractional divider 1 */
DAIOFDCR1 &= ~0x01;
/* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
MADD is 0x48(72), MSUB is 0xE8(232). where m = 0x60 and
n = 0x18. FDR is divided by 4. */
config = (((DAIOFDCR1_MSUB << 8) | DAIOFDCR1_MADD) << 3) | (0x1 << 2) | (0x1 << 1);
DAIOFDCR1 = config;
/* Clear Reset(FDRES) bit */
config &= ~0x2;
DAIOFDCR1 = config;
/* Set RUN bit(FDRUN). */
config |= 0x1;
DAIOFDCR1 = config;
/* Enable Select Register setting. ESR with 3 bit fields.
bit 0 ESR_EN is 1 causing spreading stage output clock under
the control of the fractional divider, which runs slower
than the selection stage clock. ESR_SEL, bits 3:1 is 1, FDR1 is
selected for DDAC ESR2, DADC ESR1, DADC ESR2. */
DDACESR2 = (0x1<<1) | (0x1<<0);
DADCESR1 = (0x1<<1) | (0x1<<0);
DADCESR2 = (0x1<<1) | (0x1<<0);
/* Clear RUN bit in FDCR, fractional divider 2 */
DAIOFDCR2 &= ~0x01;
/* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
MADD is 0x78(120), MSUB is 0xF8(248). where m = 0x80 and
n = 0x08. FDR is divided by 16. */
config = (((DAIOFDCR2_MSUB << 8) | DAIOFDCR2_MADD) << 3) | (0x1 << 2) | (0x1 << 1);
DAIOFDCR2 = config;
/* Clear Reset(FDRES) bit */
config &= ~0x2;
DAIOFDCR2 = config;
/* Set RUN bit(FDRUN). */
config |= 0x1;
DAIOFDCR2 = config;
/* Enable Select Register setting. ESR with 3 bit fields.
bit 0 ESR_EN is 1 causing spreading stage output clock under
the control of the fractional divider, which runs slower
than the selection stage clock. ESR_SEL, bits 3:1 is 2, FDR2 is
selected for DAI ESR1. */
// DAIESR1 = (0x2<<1) | (0x1<<0);
/* Clear RUN bit in FDCR, fractional divider 3 */
DAIOFDCR3 &= ~0x01;
/* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
MADD is 0x48(72), MSUB is 0xB8(184). where m = 0x90 and
n = 0x48. FDR is divided by 2. */
config = (((DAIOFDCR3_MSUB << 8) | DAIOFDCR3_MADD) << 3) | (0x1 << 2) | (0x1 << 1);
DAIOFDCR3 = config;
/* Clear Reset(FDRES) bit */
config &= ~0x2;
DAIOFDCR3 = config;
/* Set RUN bit(FDRUN). */
config |= 0x1;
DAIOFDCR3 = config;
/* Enable Select Register setting. ESR with 3 bit fields.
bit 0 ESR_EN is 1 causing spreading stage output clock under
the control of the fractional divider, which runs slower
than the selection stage clock. ESR_SEL, bits 3:1 is 3, FDR3 is
selected for DAO ESR1. */
DAOESR1 = (0x3<<1) | (0x1<<0);
/* Clear RUN bit in FDCR, fractional divider 4 */
DAIOFDCR4 &= ~0x01;
/* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
MADD is 0x1FF(511), MSUB is 0x3FF(1023). where m = 0x200 and
n = 0x001. FDR is divided by 512. */
config = (((DAIOFDCR4_MSUB << 10) | DAIOFDCR4_MADD) << 3) | (0x1 << 2) | (0x1 << 1);
DAIOFDCR4 = config;
/* Clear Reset(FDRES) bit */
config &= ~0x2;
DAIOFDCR4 = config;
/* Set RUN bit(FDRUN). */
config |= 0x1;
DAIOFDCR4 = config;
/* Enable Select Register setting. ESR with 3 bit fields.
bit 0 ESR_EN is 1 causing spreading stage output clock under
the control of the fractional divider, which runs slower
than the selection stage clock. ESR_SEL, bits 3:1 is 4, FDR4 is
selected for DA1 ESR2, DAO ESR2. */
// DAIESR2 = (0x4<<1) | (0x1<<0);
DAOESR2 = (0x4<<1) | (0x1<<0);
/* Clear RUN bit in FDCR, fractional divider 5 */
DAIOFDCR5 &= ~0x01;
/* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
MADD is 0x78(120), MSUB is 0xF8(248). where m = 0x80 and
n = 0x08. FDR is divided by 16. */
config = (((DAIOFDCR5_MSUB << 8) | DAIOFDCR5_MADD) << 3) | (0x1 << 2) | (0x1 << 1);
DAIOFDCR5 = config;
/* Clear Reset(FDRES) bit */
config &= ~0x2;
DAIOFDCR5 = config;
/* Set RUN bit(FDRUN). */
config |= 0x1;
DAIOFDCR5 = config;
/* Enable Select Register setting. ESR with 3 bit fields.
bit 0 ESR_EN is 1 causing spreading stage output clock under
the control of the fractional divider, which runs slower
than the selection stage clock. ESR_SEL, bits 3:1 is 5, FDR5 is
selected for DAI ESR1. */
DAOESR3 = (0x5<<1) | (0x1<<0);
/* Base Control Register, set bit 0(FDRUN) to start all the FDRs. */
DAIOBCR = 0x1;
if ( install_IRQ(16, 1, DAI_ISR ) == FALSE )
{
while ( 1 ); /* Fatal error due to ISR installation failure */
}
INT_REQ16=(1<<28)|(1<<27)|(1<<26)|(1<<16)|0x1;
INT_VECTOR0=IRQ_TABLE_BASE & MASK_INDEX;
SAIMASK1 = 0x3EF;
while (1);
return 0;
}
/*****************************************************************************
** End Of File
*****************************************************************************/
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