lpc28xx.s

nxp的LPC2888处理器的示例代码.

;//       <o7.0..3> UARTFSR2: Side 2 UART Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o8.0..3> DAIOFSR2: Side 2 DAIO Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//       <o9.0..3> DAIFSR2: Side 2 DAI Clock Selection
;//                     <0=> 32 kHz oscillator <1=> Fast oscillator <2=> MCI Clock pin
;//                     <3=> DAI BCLK pin      <4=> DAI WS pin      <7=> High Speed PLL
;//                     <8=> Main PLL
;//     </h>
;//   </h>
SYSFSR2_Val      EQU    0x00000008
APB0FSR2_Val     EQU    0x00000001
APB1FSR2_Val     EQU    0x00000001
APB3FSR2_Val     EQU    0x00000001
DCDCFSR2_Val     EQU    0x00000001
RTCFSR2_Val      EQU    0x00000000
MCIFSR2_Val      EQU    0x00000001
UARTFSR2_Val     EQU    0x00000008
DAIOFSR2_Val     EQU    0x00000001
DAIFSR2_Val      EQU    0x00000001

;// </e> Clock Configuration


;----------------------- CODE --------------------------------------------------

                PRESERVE8
                
; - Flash Marker ---------------------------------------------------------------

; Area Definition for Flash User Program Valid Marker
                
                IF      :DEF:NO_FLASHMARKER
                ELSE

                AREA    |.ARM.__AT_0x104FF800|, CODE, READONLY
                ARM

                DCD     0xAA55AA55

                ENDIF


; - Starup Code ----------------------------------------------------------------
				IMPORT  IRQ_Handler			; IRQ interrupt handler
				IMPORT  FIQ_Handler			; Fast interrupt exceptions handler 

; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    RESET, CODE, READONLY
                ARM

; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC,Reset_Addr         
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                NOP
                LDR     PC,IRQ_Addr     
                LDR     PC,FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0               ; Reserved Address
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
;IRQ_Handler     B       IRQ_Handler
;FIQ_Handler     B       FIQ_Handler


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   


; Clock Setup ------------------------------------------------------------------

                IF      CLOCK_SETUP != 0
                LDR     R0, =CGU_BASE

                IF      LPPLL_SETUP != 0          ; If Low Power PLL is used
;                MOV     R1, #1
;                STR     R1, [R0, #LPPDN_OFS]
                MOV     R1, #LPFIN_Val
                STR     R1, [R0, #LPFIN_OFS]
                MOV     R1, #LPMSEL_Val
                STR     R1, [R0, #LPMSEL_OFS]
                MOV     R1, #LPPSEL_Val
                STR     R1, [R0, #LPPSEL_OFS]
                MOV     R1, #LPMBYP_Val
                STR     R1, [R0, #LPMBYP_OFS]
                MOV     R1, #LPDBYP_Val
                STR     R1, [R0, #LPDBYP_OFS]
                MOV     R1, #0
                STR     R1, [R0, #LPPDN_OFS]
LPPLL_Loop      LDR     R1, [R0, #LPLOCK_OFS]     ; Wait for lock
                ANDS    R1, R1, #LPLOCK_ON
                BEQ     LPPLL_Loop
                ENDIF

                ; Switch to selected clocks
                LDR     R0, =CGUSWBOX_BASE
                MOV     R1, #SYSFSR2_Val
                STR     R1, [R0, #SYSFSR2_OFS]
                MOV     R1, #APB0FSR2_Val
                STR     R1, [R0, #APB0FSR2_OFS]
                MOV     R1, #APB1FSR2_Val
                STR     R1, [R0, #APB1FSR2_OFS]
                MOV     R1, #APB3FSR2_Val
                STR     R1, [R0, #APB3FSR2_OFS]
                MOV     R1, #DCDCFSR2_Val
                STR     R1, [R0, #DCDCFSR2_OFS]
                MOV     R1, #RTCFSR2_Val
                STR     R1, [R0, #RTCFSR2_OFS]
                MOV     R1, #MCIFSR2_Val
                STR     R1, [R0, #MCIFSR2_OFS]
                MOV     R1, #UARTFSR2_Val
                STR     R1, [R0, #UARTFSR2_OFS]
                MOV     R1, #DAIOFSR2_Val
                STR     R1, [R0, #DAIOFSR2_OFS]
                MOV     R1, #DAIFSR2_Val
                STR     R1, [R0, #DAIFSR2_OFS]
                MOV     R1, #2
                STR     R1, [R0, #SYSSCR_OFS]
                ENDIF


; Setup Stack for each mode ----------------------------------------------------

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size

; Enter the C code -------------------------------------------------------------

                IMPORT  __main
                LDR     R0, =__main
                BX      R0


; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR

                END