target.c

nxp的LPC2888处理器的示例代码.

/*****************************************************************************
 *   target.c:  Target C file for NXP LPC288x Family Microprocessors
 *
 *   Copyright(C) 2006, NXP Semiconductor
 *   All rights reserved.
 *
 *   History
 *   2007.02.01  ver 1.00    Prelimnary version, first Release
 *
*****************************************************************************/
#include "LPC288x.h"
#include "type.h"
#include "irq.h"
#include "target.h"

/******************************************************************************
** Function name:		ConfigurePLL
**
** Descriptions:		Initialize the target board before running the main() 
**				function; User may change it as needed, but may not 
**				deleted it.
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void ConfigurePLL( void )
{
  LPFIN = 0x01;
  LPMSEL = 4;
  LPPSEL = 1;
  LPPDN = 0;
  while ( !(LPLOCK & (0x01)));	// Wait until it's locked
  SYSFSR1 = 0x08;				// Select MAIN PLL
  return;
}

/******************************************************************************
** Function name:		ConfigureFDR0
**
** Descriptions:		Configure FDR0, most of the ESR is under
**						the control of FDR0. Check the list of the
**						ESRs configured in this module. All the 
**						HCLK of these ESR peripherals is 1/2 of
**						CCLK. 
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void ConfigureFDR0( void )
{
  DWORD config;

  /* Clear RUN bit in FDCR, fractional divider 0 */
  SYSFDCR0 &= ~0x01;
  
  /* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
  MADD is 0x48(72), MSUB is 0xB8(184), where m = 0x90 and n = 0x48. 
  FDR is divided by 2. */
  config =  (((SYSFDCR0_MSUB << 8) | SYSFDCR0_MADD) << 3) 
  		| (0x1 << 2) | (0x1 << 1);
  SYSFDCR0 = config;
  
  /* Clear Reset(FDRES) bit */
  config &= ~0x2;
  SYSFDCR0 = config;

  /* Set RUN bit(FDRUN). */   
  config |= 0x1;
  SYSFDCR0 = config;

  /* Enable Select Register setting. ESR with 3 bit fields.
  bit 0 ESR_EN is 1 causing spreading stage output clock under
  the control of the fractional divider, which runs slower
  than the selection stage clock. ESR_SEL, bit 1 is 0, FDR0 is 
  selected. */
  APB0ESR0 = 0x1<<0;
  APB1ESR0 = 0x1<<0;
  APB2ESR0 = 0x1<<0;
  APB3ESR0 = 0x1<<0;
  
  MMIOESR0 = 0x1<<0;
  AHB0ESR  = 0x1<<0;
  MCIESR0  = 0x1<<0;
  UARTESR0 = 0x1<<0;
  FLSHESR0 = 0x1<<0;
  FLSHESR1 = 0x1<<0;
  FLSHESR2 = 0x1<<0;
  LCDESR0  = 0x1<<0;
  DMAESR0  = 0x1<<0;
  DMAESR1  = 0x1<<0;
  USBESR0  = 0x1<<0;

  /* It's important that CPUESR0, the main processor clock, should not 
  be set, or the processor clock(CCLK) will be cut to half as well. */  
  CPUESR1  = 0x1<<0;
  CPUESR2  = 0x1<<0; 
  RAMESR   = 0x1<<0;
  ROMESR   = 0x1<<0;
  EMCESR0  = 0x1<<0;
  MMIOESR1 = 0x1<<0;
  return;
}

/******************************************************************************
** Function name:		ConfigureFDR1
**
** Descriptions:		Configure FDR1
**						Only MCIESR1 is under the control of FDR1. 
**						MCI MCLK is 1/4 of CCLK.
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void ConfigureFDR1( void )
{
  DWORD config;

   /* Clear RUN bit in FDCR, fractional divider 1 */
  SYSFDCR1 &= ~0x01;
  
  /* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
  MADD is 0x48(72), MSUB is 0xE8(232), where m = 0x60, n = 0x18. 
  FDR is divided by 4. */
  config =  (((SYSFDCR1_MSUB << 8) | SYSFDCR1_MADD) << 3) 
  		| (0x1 << 2) | (0x1 << 1);
  SYSFDCR1 = config;
  
  /* Clear Reset(FDRES) bit */
  config &= ~0x2;
  SYSFDCR1 = config;

  /* Set RUN bit(FDRUN). */   
  config |= 0x1;
  SYSFDCR1 = config;

  /* Enable Select Register setting. ESR with 3 bit fields.
  bit 0 ESR_EN is 1 causing spreading stage output clock under
  the control of the fractional divider, which runs slower
  than the selection stage clock. ESR_SEL, bit 1 is 1, FDR1 is 
  selected for MCI ESR1. */
  MCIESR1 = (0x1<<1) | (0x1<<0);
  return;
}

/******************************************************************************
** Function name:		ConfigureFDR3
**
** Descriptions:		Configure FDR3
**						Only LCDESR1 is under the control of FDR3.
**						LCD CLK is 1/10 of CCLK.
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void ConfigureFDR3( void )
{
  DWORD config;

   /* Clear RUN bit in FDCR, fractional divider 3 */
  SYSFDCR3 &= ~0x01;
  
  /* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
  MADD is 0x48(72), MSUB is 0xF8(248), where m = 0x50, n = 0x8. 
  FDR is divided by 10. */
  config =  (((SYSFDCR3_MSUB << 8) | SYSFDCR3_MADD) << 3) 
  		| (0x1 << 2) | (0x1 << 1);
  SYSFDCR3 = config;
  
  /* Clear Reset(FDRES) bit */
  config &= ~0x2;
  SYSFDCR3 = config;

  /* Set RUN bit(FDRUN). */   
  config |= 0x1;
  SYSFDCR3 = config;

  /* Enable Select Register setting. ESR with 3 bit fields.
  bit 0 ESR_EN is 1 causing spreading stage output clock under
  the control of the fractional divider, which runs slower
  than the selection stage clock. ESR_SEL, bit 1 is 1, FDR3 is 
  selected for LCD ESR1. */
  LCDESR1 = (0x3<<1) | (0x1<<0);
  return;
}

/******************************************************************************
** Function name:		ConfigureFDR5
**
** Descriptions:		Configure FDR5
**						Only EMCESR1 is under the control of FDR5.
**						EMC2 CLK is 1/2 of CCLK. This EMC can be
**						merged with FDR0 as all the peripherals
**						on FDR0 is 1/2 of the CCLK as well.
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void ConfigureFDR5( void )
{
  DWORD config;

  /* Clear RUN bit in FDCR, fractional divider 5 */
  SYSFDCR5 &= ~0x01;
  
  /* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit,
  MADD is 0x48(72), MSUB is 0xB8(184). where m = 0x90 and 
  n = 0x48. FDR is divided by 2. */
  config =  (((SYSFDCR5_MSUB << 8) | SYSFDCR5_MADD) << 3) 
  		| (0x1 << 2) | (0x1 << 1);
  SYSFDCR5 = config;
  
  /* Clear Reset(FDRES) bit */
  config &= ~0x2;
  SYSFDCR5 = config;

  /* Set RUN bit(FDRUN). */   
  config |= 0x1;
  SYSFDCR5 = config;

  /* Enable Select Register setting. ESR with 3 bit fields.
  bit 0 ESR_EN is 1 causing spreading stage output clock under
  the control of the fractional divider, which runs slower
  than the selection stage clock. ESR_SEL, bit 1 is 1, FDR5 is 
  selected for EMC ESR1. */
  EMCESR1 = (0x5<<1) | (0x1<<0);
  return;
}

/******************************************************************************
** Function name:	ConfigureCGU
**
** Descriptions:	Initialize the target board before running the main() 
**					function; User may change it as needed.
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void ConfigureCGU( void )
{
  /* Power Control register, set ENOUT_EN bit that the spreading 
  stage places its enable status on the internal output. */   
  CPUPCR2 |= (0x1 << 4);
  
  /* Disable Fractional Divider in the Base Control register. */ 
  SYSBCR = 0;

  ConfigureFDR0();	/* Majority of ESRs are under FDR0 control. */

  ConfigureFDR1();	/* MCI ESR1 is under FDR1 control. */

  ConfigureFDR3();	/* LCD ESR1 is under FDR3 control. */

  ConfigureFDR5();	/* EMC ESR1 is under FDR5 control. */

  /* Base Control Register, set bit 0(FDRUN) to start all the FDRs. */
  SYSBCR = 0x1;

  /* In the startup, lpc28xx.s, only SYSSCR is set for side 2,
  in order not to modify Keil's LPC28xx.s startup file, the UART
  clock setting is added here. If not switch side, below line can
  be enabled, using side1, and main PLL, which has the same effect. */
  UARTSCR = 0x02;		/* Switch to side 2, main PLL */
//  UARTFSR1 = 0x08;	/* Side 1, main PLL */

  RTCSCR = 0x02;		/* Switch to side 2, 32Khz. */
  return;
}

/******************************************************************************
** Function name:		TargetResetInit
**
** Descriptions:		Initialize the target board before running the main() 
**				function; User may change it as needed, but may not 
**				deleted it.
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void TargetResetInit(void)
{
  /* If the Keil MDK is used, their startup file has all the
  PLL setting done in the assmebly file, no need to call 
  ConfigurePLL() again to reset PLL. In any other startup file,
  TargetResetInit() should include ConfigurePLL() module. */  
//  ConfigurePLL();

  /* Configure all the fractional dividers. */
  ConfigureCGU();

  init_interrupt();

  /* Initalizing Cache Controller */
  CACHE_SETTINGS=0x1;	/* Reset the cache */
  CACHE_SETTINGS=0x0;	/* De-assert reset to the cache controller */
  while((CACHE_RST_STAT) & 0x1){}	/* Wait for reset to complete */
  CACHE_PAGE_CTRL=0x1;				/* Enable virtual page 0 */
#ifdef __FLASH
  ADDRESS_PAGE_0=(FLASH_ADDR >>21); /* Prepare virtual address */
#else
  ADDRESS_PAGE_0=(RAM_ADDR >>21); 	/* Prepare virtual address */
#endif
//  CACHE_SETTINGS=0x16;				/* Enable caching */
  CACHE_SETTINGS=0x06;				/* Enable caching */	
  return;
}

/******************************************************************************
**                            End Of File
******************************************************************************/