lpc318x.h

nxp的ARM9处理器LPC3180代码,提供了几乎所有的外设示例程序.

#define SPI2_GLOBAL	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x000))
#define SPI2_CON	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x004))
#define SPI2_FRM	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x008))
#define SPI2_IER	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x00C))
#define SPI2_STAT	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x010))
#define SPI2_DAT	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x014))
#define SPI2_TIM_CTRL	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x400))
#define SPI2_TIM_COUNT	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x404))
#define SPI2_TIM_STAT	(*(volatile unsigned long *)(SPI2_BASE_ADDR + 0x408))


/* SD Card Interface */
#define SD_BASE_ADDR	0x20098000
#define SD_POWER	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x00))
#define SD_CLOCK	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x04))
#define SD_ARGUMENT	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x08))
#define SD_COMMAND	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x0C))
#define SD_RESPCMD	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x10))
#define SD_RESPONSE0	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x14))
#define SD_RESPONSE1	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x18))
#define SD_RESPONSE2	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x1C))
#define SD_RESPONSE3	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x20))
#define SD_DATATIMER	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x24))
#define SD_DATALENGTH	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x28))
#define SD_DATACTRL	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x2C))
#define SD_DATACNT	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x30))
#define SD_STATUS	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x34))
#define SD_CLEAR	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x38))
#define SD_MASK0	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x3C))
#define SD_MASK1	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x40))
#define SD_FIFOCNT	(*(volatile unsigned long *)(SD_BASE_ADDR + 0x48))
/* Note: for FIFO register, the addr. is 0x20098080 through 0x200980BC */
#define SD_FIFO		(*(volatile unsigned long *)(SD_BASE_ADDR + 0x80))


/* I2C Interface 0 */
#define I2C0_BASE_ADDR		0x400A0000
#define I2C0_RX		(*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
#define I2C0_TX		(*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
#define I2C0_STS	(*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
#define I2C0_CTRL	(*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
#define I2C0_CLKH	(*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
#define I2C0_CLKL	(*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))

/* I2C Interface 1 */
#define I2C1_BASE_ADDR		0x400A8000
#define I2C1_RX		(*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
#define I2C1_TX		(*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
#define I2C1_STS	(*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
#define I2C1_CTRL	(*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
#define I2C1_CLKH	(*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
#define I2C1_CLKL	(*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))


/* Keyboard Scan controller interface */
#define KS_BASE_ADDR		0x40050000
#define KS_DEB		(*(volatile unsigned long *)(KS_BASE_ADDR + 0x00))
#define KS_STATE_COND	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x04))
#define KS_IRQ		(*(volatile unsigned long *)(KS_BASE_ADDR + 0x08))
#define KS_SCAN_CTL	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x0C))
#define KS_FAST_TST	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x10))
#define KS_MATRIX_DIM	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x14))
#define KS_DATA0	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x40))
#define KS_DATA1	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x44))
#define KS_DATA2	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x48))
#define KS_DATA3	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x4C))
#define KS_DATA4	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x50))
#define KS_DATA5	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x54))
#define KS_DATA6	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x58))
#define KS_DATA7	(*(volatile unsigned long *)(KS_BASE_ADDR + 0x5C))


/* High-speed Timer  */
#define HSTIM_BASE_ADDR		0x40038000
#define HSTIM_INT	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x00))
#define HSTIM_CTRL	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x04))
#define HSTIM_COUNTER	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x08))
#define HSTIM_PMATCH	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x0C))
#define HSTIM_PCOUNT	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x10))
#define HSTIM_MCTRL	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x14))
#define HSTIM_MATCH0	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x18))
#define HSTIM_MATCH1	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x1C))
#define HSTIM_MATCH2	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x20))
#define HSTIM_CCR	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x28))
#define HSTIM_CR0	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x2C))
#define HSTIM_CR1	(*(volatile unsigned long *)(HSTIM_BASE_ADDR + 0x30))


/* Millisecond Timer */
#define MSTIM_BASE_ADDR		0x40034000
#define MSTIM_INT	(*(volatile unsigned long *)(MSTIM_BASE_ADDR + 0x00))
#define MSTIM_CTRL	(*(volatile unsigned long *)(MSTIM_BASE_ADDR + 0x04))
#define MSTIM_COUNTER	(*(volatile unsigned long *)(MSTIM_BASE_ADDR + 0x08))
#define MSTIM_MCTRL	(*(volatile unsigned long *)(MSTIM_BASE_ADDR + 0x14))
#define MSTIM_MATCH0	(*(volatile unsigned long *)(MSTIM_BASE_ADDR + 0x18))
#define MSTIM_MATCH1	(*(volatile unsigned long *)(MSTIM_BASE_ADDR + 0x1C))


/* Real Time Clock */
#define RTC_BASE_ADDR		0x40024000
#define RTC_UCOUNT	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
#define RTC_DCOUNT	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
#define RTC_MATCH0	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
#define RTC_MATCH1	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
#define RTC_CTRL	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
#define RTC_INTSTAT	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
#define RTC_KEY		(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
#define RTC_SRAM	(*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))


/* Watchdog timer */
#define WDTIM_BASE_ADDR		0x4003C000
#define WDTIM_INT	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x00))
#define WDTIM_CTRL	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x04))
#define WDTIM_COUNTER	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x08))
#define WDTIM_MCTRL	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x0C))
#define WDTIM_MATCH0	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x10))
#define WDTIM_EMR	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x14))
#define WDTIM_PULSE	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x18))
#define WDTIM_RES	(*(volatile unsigned long *)(WDTIM_BASE_ADDR + 0x1C))


/* A/D Converter */
#define ADC_BASE_ADDR		0x40048000
#define ADSTAT		(*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
#define ADSEL		(*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
#define ADCON		(*(volatile unsigned long *)(AD1_BASE_ADDR + 0x08))
#define ADDAT		(*(volatile unsigned long *)(AD1_BASE_ADDR + 0x48))


/* DMA */
#define DMAC_BASE_ADDR		0x31000000
#define DMAC_INT_STAT	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x000))
#define DMAC_INT_TCSTAT	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x004))
#define DMAC_INT_TCCLEAR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x008))
#define DMAC_INT_ERRSTAT	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x00C))
#define DMAC_INT_ERRCLR		(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x010))
#define DMAC_RAW_INT_TCSTAT	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x014))
#define DMAC_RAW_INT_ERRSTAT	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x018))
#define DMAC_ENBLD_CHNS	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x01C))
#define DMAC_SOFT_BREQ	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x020))
#define DMAC_SOFT_SREQ	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x024))
#define DMAC_SOFT_LBREQ	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x028))
#define DMAC_SOFT_LSREQ	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x02C))
#define DMAC_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x030))
#define DMAC_SYNC	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x034))

#define DMAC_C0_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x100))
#define DMAC_C0_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x104))
#define DMAC_C0_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x108))
#define DMAC_C0_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x10C))
#define DMAC_C0_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x110))

#define DMAC_C1_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x120))
#define DMAC_C1_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x124))
#define DMAC_C1_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x128))
#define DMAC_C1_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x12C))
#define DMAC_C1_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x130))

#define DMAC_C2_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x140))
#define DMAC_C2_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x144))
#define DMAC_C2_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x148))
#define DMAC_C2_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x14C))
#define DMAC_C2_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x150))

#define DMAC_C3_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x160))
#define DMAC_C3_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x164))
#define DMAC_C3_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x168))
#define DMAC_C3_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x16C))
#define DMAC_C3_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x170))

#define DMAC_C4_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x180))
#define DMAC_C4_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x184))
#define DMAC_C4_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x188))
#define DMAC_C4_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x18C))
#define DMAC_C4_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x190))

#define DMAC_C5_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1A0))
#define DMAC_C5_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1A4))
#define DMAC_C5_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1A8))
#define DMAC_C5_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1AC))
#define DMAC_C5_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1B0))

#define DMAC_C6_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1C0))
#define DMAC_C6_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1C4))
#define DMAC_C6_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1C8))
#define DMAC_C6_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1CC))
#define DMAC_C6_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1D0))

#define DMAC_C7_SRC_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1E0))
#define DMAC_C7_DEST_ADDR	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1E4))
#define DMAC_C7_LLI	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1E8))
#define DMAC_C7_CONTROL	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1EC))
#define DMAC_C7_CONFIG	(*(volatile unsigned long *)(DMAC_BASE_ADDR + 0x1F0))


#endif  // __LPC318x_H