lpc318x.h

nxp的ARM9处理器LPC3180代码,提供了几乎所有的外设示例程序.

/******************************************************************************
 *   LPC318X.h:  Header file for Philips LPC318x Family Microprocessors
 *   The header file is the super set of all hardware definition of the 
 *   peripherals for the LPC318x family microprocessor.
 *
 *   Copyright(C) 2006, Philips Semiconductor
 *   All rights reserved.

 *   History
 *   2005.10.01  ver 1.00    Prelimnary version, first Release
 *
******************************************************************************/

#ifndef __LPC318x_H
#define __LPC318x_H


/* System Control */
#define SYSCTRL_BASE_ADDR	0x40004000
#define BOOT_MAP	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x14))


/* Clock and Power Control */
#define CLK_PM_BASE_ADDR	0x40004000
#define PWR_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x44))
#define OSC_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x4C))
#define SYSCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x50))
#define PLL397_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x48))	
#define HCLKPLL_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x58))
#define HCLKDIV_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x40))
#define TEST_CLK	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xA4))
#define AUTOCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xEC))

#define START_ER_INT	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x20))
#define START_ER_PIN	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x30))
#define START_RSR_INT	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x24))
#define START_RSR_PIN	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x34))
#define START_SR_INT	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x28))
#define START_SR_PIN	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x38))
#define START_APR_INT	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x2C))
#define START_APR_PIN	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x3C))

#define DMACLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xE8))
#define UARTCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xE4))
#define USBCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x64))
#define MS_CTRL		(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0x80))
#define I2CCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xAC))
#define KEYCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xB0))
#define ADCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xB4))
#define PWMCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xB8))
#define TIMCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xBC))
#define SPI_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xC4))
#define FLASHCLK_CTRL	(*(volatile unsigned long *)(CLK_PM_BASE_ADDR + 0xC8))


/* SDRAM Control register */
#define SDRAM_CLK_BASE_ADDR	0x40004000
#define SDRAMCLK_CTRL	(*(volatile unsigned long *)(SDRAM_CLK_BASE_ADDR + 0x68))

#define SDRAM_BASE_ADDR		0x31080000
#define MPMCControl	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x00))
#define MPMCStatus	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x04))
#define MPMCConfig	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x08))
#define MPMCDynamicControl	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x20))
#define MPMCDynamicRefresh	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x24))
#define MPMCDynamicReadConfig	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x28))
#define MPMCDynamicRP	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x30))
#define MPMCDynamicRAS	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x34))
#define MPMCDynamicSREX	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x38))
#define MPMCDynamicWR	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x44))
#define MPMCDynamicRC	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x48))
#define MPMCDynamicRFC	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x4C))
#define MPMCDynamicXSR	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x50))
#define MPMCDynamicRRD	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x54))
#define MPMCDynamicMRD	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x58))
#define MPMCDynamicCDLR	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x5C))

#define MPMCDynamicConfig0	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x100))
#define MPMCDynamicRasCas0	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x104))

#define MPMCAHBControl0	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x400))
#define MPMCAHBStatus0	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x404))
#define MPMCAHBTimeout0	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x408))

#define MPMCAHBControl2	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x440))
#define MPMCAHBStatus2	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x444))
#define MPMCAHBTimeout2	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x448))

#define MPMCAHBControl3	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x460))
#define MPMCAHBStatus3	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x464))
#define MPMCAHBTimeout3	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x468))

#define MPMCAHBControl4	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x480))
#define MPMCAHBStatus4	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x484))
#define MPMCAHBTimeout4	(*(volatile unsigned long *)(SDRAM_BASE_ADDR + 0x488))

#define DDR_BASE_ADDR	0x40004000
#define DDR_LAP_NOM	(*(volatile unsigned long *)(DDR_BASE_ADDR + 0x6C))
#define DDR_LAP_COUNT	(*(volatile unsigned long *)(DDR_BASE_ADDR + 0x70))
#define DDR_CAL_DELAY	(*(volatile unsigned long *)(DDR_BASE_ADDR + 0x74))
#define RINGOSC_CTRL	(*(volatile unsigned long *)(DDR_BASE_ADDR + 0x88))


/* Interrupt Controller */
#define MIC_BASE_ADDR	0x40008000
#define MIC_ER		(*(volatile unsigned long *)(MIC_BASE_ADDR + 0x00))
#define MIC_RSR		(*(volatile unsigned long *)(MIC_BASE_ADDR + 0x04))
#define MIC_SR		(*(volatile unsigned long *)(MIC_BASE_ADDR + 0x08))
#define MIC_APR		(*(volatile unsigned long *)(MIC_BASE_ADDR + 0x0C))	
#define MIC_ATR		(*(volatile unsigned long *)(MIC_BASE_ADDR + 0x10))
#define MIC_ITR		(*(volatile unsigned long *)(MIC_BASE_ADDR + 0x14))

#define SIC1_BASE_ADDR	0x4000C000
#define SIC1_ER		(*(volatile unsigned long *)(SIC1_BASE_ADDR + 0x00))
#define SIC1_RSR	(*(volatile unsigned long *)(SIC1_BASE_ADDR + 0x04))
#define SIC1_SR		(*(volatile unsigned long *)(SIC1_BASE_ADDR + 0x08))
#define SIC1_APR	(*(volatile unsigned long *)(SIC1_BASE_ADDR + 0x0C))
#define SIC1_ATR	(*(volatile unsigned long *)(SIC1_BASE_ADDR + 0x10))
#define SIC1_ITR	(*(volatile unsigned long *)(SIC1_BASE_ADDR + 0x14))

#define SIC2_BASE_ADDR	0x40010000
#define SIC2_ER		(*(volatile unsigned long *)(SIC2_BASE_ADDR + 0x00))
#define SIC2_RSR	(*(volatile unsigned long *)(SIC2_BASE_ADDR + 0x04))
#define SIC2_SR		(*(volatile unsigned long *)(SIC2_BASE_ADDR + 0x08))
#define SIC2_APR	(*(volatile unsigned long *)(SIC2_BASE_ADDR + 0x0C))
#define SIC2_ATR	(*(volatile unsigned long *)(SIC2_BASE_ADDR + 0x10))
#define SIC2_ITR	(*(volatile unsigned long *)(SIC2_BASE_ADDR + 0x14))

#define SWI_BASE_ADDR	0x40004000
#define SW_INT		(*(volatile unsigned long *)(SWI_BASE_ADDR + 0xA8))


/* Multiple level NAND Flash */
#define MLC_BASE_ADDR	0x200B8000
#define MLC_CMD		(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x00))
#define MLC_ADDR	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x04))
#define MLC_ECC_ENC_REG	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x08))
#define MLC_ECC_DEC_REG	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x0C))
#define MLC_ECC_AUTO_ENC_REG	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x10))
#define MLC_ECC_AUTO_DEC_REG	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x14))
#define MLC_RPR		(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x18))
#define MLC_WPR		(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x1C))
#define MLC_RUBP	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x20))
#define MLC_ROBP	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x24))
#define MLC_SW_WP_ADD_LOW	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x28))
#define MLC_SW_WP_ADD_HIG	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x2C))
#define MLC_ICR		(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x30))
#define MLC_TIME_REG	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x34))
#define MLC_IRQ_MR	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x38))
#define MLC_IRQ_SR	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x3C))
#define MLC_LOCK_PR	(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x44))
#define MLC_ISR		(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x48))
#define MLC_CEH		(*(volatile unsigned long *)(MLC_BASE_ADDR + 0x4C))


/* Single level NAND Flash */
#define SLC_BASE_ADDR	0x20020000
#define SLC_DATA	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x00))
#define SLC_ADDR	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x04))
#define SLC_CMD		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x08))
#define SLC_STOP	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x0C))
#define SLC_CTRL	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x10))
#define SLC_CFG		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x14))
#define SLC_STAT	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x18))
#define SLC_INT_STAT	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x1C))
#define SLC_IEN		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x20))
#define SLC_ISR		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x24))
#define SLC_ICR		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x28))
#define SLC_TAC		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x2C))
#define SLC_TC		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x30))
#define SLC_ECC		(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x34))
#define SLC_DMA_DATA	(*(volatile unsigned long *)(SLC_BASE_ADDR + 0x38))


/* GPIOs */
#define GPIO_BASE_ADDR	0x40028000
#define PIO_INP_STATE	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
#define PIO_OUTP_SET	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
#define PIO_OUTP_CLR	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
#define PIO_OUTP_STATE	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
#define PIO_DIR_SET	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
#define PIO_DIR_CLR	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
#define PIO_DIR_STATE	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
#define PIO_SDINP_STATE	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
#define PIO_SDOUTP_SET	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x20))
#define PIO_SDOUTP_CLR	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x24))
#define PIO_MUX_SET	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x28))
#define PIO_MUX_CLR	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x2C))
#define PIO_MUX_STATE	(*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x30))


/* USB Device */
#define USB_BASE_ADDR		0x31020200

/* Device Interrupt Registers */
#define DEV_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
#define DEV_INT_EN          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
#define DEV_INT_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
#define DEV_INT_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
#define DEV_INT_PRIO        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))