📄 hardware.lst
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// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
000096F1 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
000096F2 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
000096F4 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
000096F5 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
000096F7 09 93 00 FD R1 = 0xfd00 // 16K
000096F9 19 D3 0A 70 [P_TimerA_Data] = R1
000096FB 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
000096FD 19 D3 2A 70 [P_DAC_Ctrl] = R1
000096FF 09 93 FF FF R1 = 0xffff
00009701 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00009703 40 92 R1 =0x0000 //
00009704 11 93 24 03 R1 = [R_InterruptStatus] //
00009706 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
00009708 19 D3 24 03 [R_InterruptStatus] = R1 //
0000970A 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000970C 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000970D 40 92 R1 = 0x0000 // 24MHz Fosc
0000970E 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
00009710 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009711 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
00009713 09 93 ED FC R1 = 0xfced // 15.625K
00009715 19 D3 0A 70 [P_TimerA_Data]=R1
00009717 09 93 A8 00 R1 = 0x00A8 //
00009719 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
0000971B 09 93 FF FF R1 = 0xffff
0000971D 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000971F 11 93 24 03 R1 = [R_InterruptStatus] //
00009721 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
00009723 19 D3 24 03 [R_InterruptStatus] = R1 //
00009725 19 D3 10 70 [P_INT_Ctrl] = R1 //
00009727 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
00009728 60 92 R1=0x0020;
00009729 19 D3 13 70 [P_SystemClock]=R1
0000972B 09 93 A8 00 R1 = 0x00A8; //
0000972D 19 D3 2A 70 [P_DAC_Ctrl]= R1
0000972F 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009730 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
00009732 09 93 00 FE R1 = 0xfe00; // 24K
00009734 19 D3 0A 70 [P_TimerA_Data] = R1;
00009736 09 93 FF FF R1 = 0xffff
00009738 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000973A 11 93 24 03 R1 = [R_InterruptStatus] //
0000973C 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
0000973E 19 D3 24 03 [R_InterruptStatus] = R1 //
00009740 19 D3 10 70 [P_INT_Ctrl] = R1 //
00009742 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
00009743 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
00009744 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
00009746 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009747 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
00009749 40 92 R1 = 0x0000 // Fosc/2
0000974A 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000974C 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
0000974E 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
00009750 09 93 FF FF R1 = 0xffff
00009752 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00009754 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
00009755 46 92 R1 = 0x0006
00009756 19 D3 2A 70 [P_DAC_Ctrl] = R1
00009758 09 93 00 FE R1 = 0xFE00
0000975A 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000975C 11 93 24 03 R1 = [R_InterruptStatus] //
0000975E 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
00009760 19 D3 24 03 [R_InterruptStatus] = R1 //
00009762 19 D3 10 70 [P_INT_Ctrl] = R1 //
00009764 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
00009765 09 93 A8 00 R1 = 0x00A8
00009767 19 D3 2A 70 [P_DAC_Ctrl] = R1
00009769 09 93 00 FE R1 = 0xFE00
0000976B 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000976D 11 93 24 03 R1 = [R_InterruptStatus] //
0000976F 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00009771 19 D3 24 03 [R_InterruptStatus] = R1 //
00009773 19 D3 10 70 [P_INT_Ctrl] = R1 //
00009775 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
00009776 09 93 A8 00 R1 = 0x00A8
00009778 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000977A 09 93 9A FD R1 = 0xFD9A
0000977C 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000977E 11 93 24 03 R1 = [R_InterruptStatus] //
00009780 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00009782 19 D3 24 03 [R_InterruptStatus] = R1 //
00009784 19 D3 10 70 [P_INT_Ctrl] = R1 //
00009786 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
00009787 09 93 A8 00 R1 = 0x00A8
00009789 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000978B 09 93 00 FD R1 = 0xFD00
0000978D 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000978F 11 93 24 03 R1 = [R_InterruptStatus] //
00009791 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00009793 19 D3 24 03 [R_InterruptStatus] = R1 //
00009795 19 D3 10 70 [P_INT_Ctrl] = R1 //
00009797 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
00009798 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
00009799 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000979B 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000979C 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000979E 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
000097A0 19 D3 0A 70 [P_TimerA_Data] = r1;
000097A2 75 92 r1 = 0x0035; // ADINI should be open (107)
000097A3 19 D3 15 70 [P_ADC_Ctrl] = r1;
000097A5 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
000097A7 19 D3 2A 70 [P_DAC_Ctrl] = r1;
000097A9 09 93 FF FF r1 = 0xffff;
000097AB 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
000097AD 11 93 24 03 R1 = [R_InterruptStatus] //
000097AF 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000097B1 19 D3 24 03 [R_InterruptStatus] = R1 //
000097B3 19 D3 10 70 [P_INT_Ctrl] = R1 //
000097B5 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
000097B6 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
000097B7 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
000097B9 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
000097BB 19 D3 0A 70 [P_TimerA_Data] = r1
000097BD 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
000097BE 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
000097BF 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
000097C1 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
000097C3 19 D3 0A 70 [P_TimerA_Data] = r1;
000097C5 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
000097C6 90 D4 push r1,r2 to [sp]
000097C7 11 93 17 70 r1=[P_DAC1]
000097C9 09 B3 C0 FF r1 &= ~0x003f
000097CB 09 43 00 80 cmp r1,0x8000
000097CD 0E 0E jb L_RU_NormalUp
000097CE 19 5E je L_RU_End
L_RU_DownLoop:
000097CF 40 F0 32 98 call F_Delay
000097D1 41 94 r2 = 0x0001
000097D2 1A D5 12 70 [P_Watchdog_Clear] = r2
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