sled.tan.qmsg

使用VerilogHDL语言实现硬件的开发模拟

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "sled.v" "" { Text "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/sled.v" 4 -1 0 } } { "d:/program files/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register lpm_counter:count_rtl_0\|dffs\[9\] register lpm_counter:count_rtl_0\|dffs\[19\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clock\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:count_rtl_0\|dffs\[9\]\" and destination register \"lpm_counter:count_rtl_0\|dffs\[19\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[9\] 1 REG LC10 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 19; REG Node = 'lpm_counter:count_rtl_0\|dffs\[9\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "" { lpm_counter:count_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:count_rtl_0\|dffs\[19\] 2 REG LC61 9 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC61; Fanout = 9; REG Node = 'lpm_counter:count_rtl_0\|dffs\[19\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "8.000 ns" { lpm_counter:count_rtl_0|dffs[9] lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "8.000 ns" { lpm_counter:count_rtl_0|dffs[9] lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:count_rtl_0|dffs[9] lpm_counter:count_rtl_0|dffs[19] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 28 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'clock'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "" { clock } "NODE_NAME" } "" } } { "sled.v" "" { Text "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/sled.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:count_rtl_0\|dffs\[19\] 2 REG LC61 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC61; Fanout = 9; REG Node = 'lpm_counter:count_rtl_0\|dffs\[19\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "0.000 ns" { clock lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 28 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'clock'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "" { clock } "NODE_NAME" } "" } } { "sled.v" "" { Text "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/sled.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:count_rtl_0\|dffs\[9\] 2 REG LC10 19 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC10; Fanout = 19; REG Node = 'lpm_counter:count_rtl_0\|dffs\[9\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "0.000 ns" { clock lpm_counter:count_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "8.000 ns" { lpm_counter:count_rtl_0|dffs[9] lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:count_rtl_0|dffs[9] lpm_counter:count_rtl_0|dffs[19] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[19] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[9] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock seg\[3\] lpm_counter:count_rtl_0\|dffs\[24\] 17.000 ns register " "Info: tco from clock \"clock\" to destination pin \"seg\[3\]\" through register \"lpm_counter:count_rtl_0\|dffs\[24\]\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 28 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'clock'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "" { clock } "NODE_NAME" } "" } } { "sled.v" "" { Text "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/sled.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:count_rtl_0\|dffs\[24\] 2 REG LC50 25 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC50; Fanout = 25; REG Node = 'lpm_counter:count_rtl_0\|dffs\[24\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "0.000 ns" { clock lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[24] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|dffs\[24\] 1 REG LC50 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC50; Fanout = 25; REG Node = 'lpm_counter:count_rtl_0\|dffs\[24\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "" { lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns reduce_or~1122 2 COMB LC67 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC67; Fanout = 1; COMB Node = 'reduce_or~1122'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "9.000 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1122 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns seg\[3\] 3 PIN PIN_45 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'seg\[3\]'" {  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "4.000 ns" { reduce_or~1122 seg[3] } "NODE_NAME" } "" } } { "sled.v" "" { Text "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/sled.v" 2 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "13.000 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1122 seg[3] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1122 seg[3] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}  } { { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "3.000 ns" { clock lpm_counter:count_rtl_0|dffs[24] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out lpm_counter:count_rtl_0|dffs[24] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" "" { Report "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/db/sled.quartus_db" { Floorplan "C:/Documents and Settings/zyy/桌面/Verilog hdl/静态数码显示/" "" "13.000 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1122 seg[3] } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { lpm_counter:count_rtl_0|dffs[24] reduce_or~1122 seg[3] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 25 19:45:30 2006 " "Info: Processing ended: Thu May 25 19:45:30 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}