sled.fit.eqn

使用VerilogHDL语言实现硬件的开发模拟

B1_dffs[25]_or_out = B1_dffs[25];
B1_dffs[25]_reg_input = B1_dffs[25]_p1_out $ B1_dffs[25]_or_out;
B1_dffs[25] = DFFE(B1_dffs[25]_reg_input, GLOBAL(clock), , , );


--B1_dffs[26] is lpm_counter:count_rtl_0|dffs[26] at LC54
B1_dffs[26]_p1_out = B1_dffs[25] & B1_dffs[24] & B1_dffs[23] & B1_dffs[22] & B1_dffs[21] & B1_dffs[20] & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[26]_or_out = B1_dffs[26];
B1_dffs[26]_reg_input = B1_dffs[26]_p1_out $ B1_dffs[26]_or_out;
B1_dffs[26] = DFFE(B1_dffs[26]_reg_input, GLOBAL(clock), , , );


--B1_dffs[27] is lpm_counter:count_rtl_0|dffs[27] at LC53
B1_dffs[27]_p1_out = B1_dffs[26] & B1_dffs[25] & B1_dffs[24] & B1_dffs[23] & B1_dffs[22] & B1_dffs[21] & B1_dffs[20] & B1_dffs[19] & B1_dffs[18] & B1_dffs[17] & B1_dffs[16] & B1_dffs[15] & B1_dffs[14] & B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[27]_or_out = B1_dffs[27];
B1_dffs[27]_reg_input = B1_dffs[27]_p1_out $ B1_dffs[27]_or_out;
B1_dffs[27] = DFFE(B1_dffs[27]_reg_input, GLOBAL(clock), , , );


--A1L6 is reduce_or~1100 at LC72
A1L6_p1_out = !B1_dffs[26] & !B1_dffs[27] & B1_dffs[24];
A1L6_p2_out = B1_dffs[26] & B1_dffs[27] & B1_dffs[24] & !B1_dffs[25];
A1L6_p3_out = !B1_dffs[26] & !B1_dffs[27] & B1_dffs[25];
A1L6_p4_out = !B1_dffs[27] & B1_dffs[24] & B1_dffs[25];
A1L6_or_out = A1L6_p1_out # A1L6_p2_out # A1L6_p3_out # A1L6_p4_out;
A1L6 = A1L6_or_out;


--A1L7 is reduce_or~1104 at LC73
A1L7_p1_out = B1_dffs[24] & !B1_dffs[27] & B1_dffs[25] & B1_dffs[26];
A1L7_p2_out = !B1_dffs[27] & !B1_dffs[25] & !B1_dffs[26];
A1L7_p3_out = !B1_dffs[24] & B1_dffs[27] & !B1_dffs[25] & B1_dffs[26];
A1L7_or_out = A1L7_p1_out # A1L7_p2_out # A1L7_p3_out;
A1L7 = A1L7_or_out;


--A1L8 is reduce_or~1108 at LC69
A1L8_p1_out = !B1_dffs[27] & !B1_dffs[25] & B1_dffs[26];
A1L8_p2_out = !B1_dffs[27] & B1_dffs[24];
A1L8_p3_out = !B1_dffs[25] & !B1_dffs[26] & B1_dffs[24];
A1L8_or_out = A1L8_p1_out # A1L8_p2_out # A1L8_p3_out;
A1L8 = A1L8_or_out;


--A1L9 is reduce_or~1113 at LC51
A1L9_p1_out = B1_dffs[24] & !B1_dffs[25] & B1_dffs[26] & B1_dffs[27];
A1L9_p2_out = B1_dffs[24] & B1_dffs[25] & !B1_dffs[26] & B1_dffs[27];
A1L9_p3_out = B1_dffs[24] & !B1_dffs[25] & !B1_dffs[26] & !B1_dffs[27];
A1L9_p4_out = !B1_dffs[24] & !B1_dffs[25] & B1_dffs[26] & !B1_dffs[27];
A1L9_or_out = A1L9_p1_out # A1L9_p2_out # A1L9_p3_out # A1L9_p4_out;
A1L9 = A1L9_or_out;


--A1L01 is reduce_or~1117 at LC65
A1L01_p1_out = B1_dffs[25] & B1_dffs[26] & B1_dffs[27];
A1L01_p2_out = B1_dffs[26] & B1_dffs[27] & !B1_dffs[24];
A1L01_p3_out = B1_dffs[25] & !B1_dffs[26] & !B1_dffs[27] & !B1_dffs[24];
A1L01_or_out = A1L01_p1_out # A1L01_p2_out # A1L01_p3_out;
A1L01 = A1L01_or_out;


--A1L11 is reduce_or~1122 at LC67
A1L11_p1_out = !B1_dffs[25] & !B1_dffs[27] & !B1_dffs[26] & B1_dffs[24];
A1L11_p2_out = !B1_dffs[25] & !B1_dffs[27] & B1_dffs[26] & !B1_dffs[24];
A1L11_p3_out = B1_dffs[25] & B1_dffs[27] & !B1_dffs[26] & !B1_dffs[24];
A1L11_p4_out = B1_dffs[25] & B1_dffs[26] & B1_dffs[24];
A1L11_or_out = A1L11_p1_out # A1L11_p2_out # A1L11_p3_out # A1L11_p4_out;
A1L11 = A1L11_or_out;


--A1L21 is reduce_or~1127 at LC49
A1L21_p1_out = B1_dffs[26] & !B1_dffs[24] & B1_dffs[25];
A1L21_p2_out = B1_dffs[26] & !B1_dffs[24] & B1_dffs[27];
A1L21_p3_out = B1_dffs[26] & B1_dffs[24] & !B1_dffs[25] & !B1_dffs[27];
A1L21_p4_out = B1_dffs[24] & B1_dffs[25] & B1_dffs[27];
A1L21_or_out = A1L21_p1_out # A1L21_p2_out # A1L21_p3_out # A1L21_p4_out;
A1L21 = A1L21_or_out;


--~VCC~0 is ~VCC~0 at LC75
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0 at LC77
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1 at LC80
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2 at LC83
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3 at LC85
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--clock is clock at PIN_83
--operation mode is input

clock = INPUT();


--seg[7] is seg[7] at PIN_50
--operation mode is output

seg[7] = OUTPUT(~VCC~0);


--sl[0] is sl[0] at PIN_51
--operation mode is output

sl[0] = OUTPUT(~GND~0);


--sl[1] is sl[1] at PIN_52
--operation mode is output

sl[1] = OUTPUT(~GND~1);


--sl[2] is sl[2] at PIN_54
--operation mode is output

sl[2] = OUTPUT(~GND~2);


--sl[3] is sl[3] at PIN_55
--operation mode is output

sl[3] = OUTPUT(~GND~3);


--seg[4] is seg[4] at PIN_46
--operation mode is output

seg[4] = OUTPUT(A1L8);


--seg[5] is seg[5] at PIN_48
--operation mode is output

seg[5] = OUTPUT(A1L6);


--seg[6] is seg[6] at PIN_49
--operation mode is output

seg[6] = OUTPUT(A1L7);


--seg[0] is seg[0] at PIN_40
--operation mode is output

seg[0] = OUTPUT(A1L9);


--seg[1] is seg[1] at PIN_41
--operation mode is output

seg[1] = OUTPUT(A1L21);


--seg[2] is seg[2] at PIN_44
--operation mode is output

seg[2] = OUTPUT(A1L01);


--seg[3] is seg[3] at PIN_45
--operation mode is output

seg[3] = OUTPUT(A1L11);