dled.tan.rpt

使用VerilogHDL语言实现硬件的开发模拟

; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[4]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[5]  ; lpm_counter:count_rtl_0|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[4]  ; lpm_counter:count_rtl_0|dffs[4]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[3]  ; lpm_counter:count_rtl_0|dffs[3]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[2]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[2]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[2]  ; lpm_counter:count_rtl_0|dffs[2]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[1]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[1]  ; lpm_counter:count_rtl_0|dffs[1]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; lpm_counter:count_rtl_0|dffs[0]  ; lpm_counter:count_rtl_0|dffs[0]  ; clock      ; clock    ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+----------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------+
; tco                                                                                        ;
+-------+--------------+------------+----------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                             ; To     ; From Clock ;
+-------+--------------+------------+----------------------------------+--------+------------+
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[3]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[3]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[6] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[6] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[4] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[4] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[2] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[2] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[0] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[0] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[2]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[2]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[1]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[1]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; sl[0]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; sl[0]  ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[5] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[5] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[13] ; seg[3] ; clock      ;
; N/A   ; None         ; 17.000 ns  ; lpm_counter:count_rtl_0|dffs[14] ; seg[3] ; clock      ;
+-------+--------------+------------+----------------------------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu May 25 20:24:28 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dled -c dled
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 76.92 MHz between source register "lpm_counter:count_rtl_0|dffs[0]" and destination register "lpm_counter:count_rtl_0|dffs[14]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 15; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 12; REG Node = 'lpm_counter:count_rtl_0|dffs[14]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 12; REG Node = 'lpm_counter:count_rtl_0|dffs[14]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clock" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 15; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clock" to destination pin "sl[3]" through register "lpm_counter:count_rtl_0|dffs[13]" is 17.000 ns
    Info: + Longest clock path from clock "clock" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC2; Fanout = 13; REG Node = 'lpm_counter:count_rtl_0|dffs[13]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 13; REG Node = 'lpm_counter:count_rtl_0|dffs[13]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC85; Fanout = 1; COMB Node = 'reduce_or~34'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'sl[3]'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 25 20:24:30 2006
    Info: Elapsed time: 00:00:04