dled.map.rpt

使用VerilogHDL语言实现硬件的开发模拟

; look_add.inc                     ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf                      ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;
; look_add.tdf                     ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/look_add.tdf            ;
; altshift.tdf                     ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/altshift.tdf            ;
; lpm_constant.tdf                 ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/lpm_constant.tdf        ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 27                   ;
; Total registers      ; 15                   ;
; I/O pins             ; 13                   ;
; Maximum fan-out node ; clock                ;
; Maximum fan-out      ; 15                   ;
; Total fan-out        ; 165                  ;
; Average fan-out      ; 4.13                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                              ;
+------------------------------+------------+------+-------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name           ;
+------------------------------+------------+------+-------------------------------+
; |dled                        ; 27         ; 13   ; |dled                         ;
;    |lpm_counter:count_rtl_0| ; 15         ; 0    ; |dled|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+-------------------------------+


+--------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:count_rtl_0 ;
+------------------------+----------+--------------------------------------+
; Parameter Name         ; Value    ; Type                                 ;
+------------------------+----------+--------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                       ;
; LPM_WIDTH              ; 37       ; Untyped                              ;
; LPM_DIRECTION          ; UP       ; Untyped                              ;
; LPM_MODULUS            ; 0        ; Untyped                              ;
; LPM_AVALUE             ; UNUSED   ; Untyped                              ;
; LPM_SVALUE             ; UNUSED   ; Untyped                              ;
; DEVICE_FAMILY          ; MAX7000S ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                              ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                   ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                   ;
; CARRY_CNT_EN           ; SMART    ; Untyped                              ;
; LABWIDE_SCLR           ; ON       ; Untyped                              ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                              ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                              ;
+------------------------+----------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/zyy/桌面/Verilog hdl/动态数码显示/dled.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu May 25 20:24:04 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dled -c dled
Info: Found 1 design units, including 1 entities, in source file dled.v
    Info: Found entity 1: dled
Info: Elaborating entity "dled" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=37) from the following logic: "count[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Ignored 15 buffer(s)
    Info: Ignored 15 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seg[1]" stuck at GND
    Warning: Pin "seg[7]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 40 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 12 output pins
    Info: Implemented 27 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu May 25 20:24:14 2006
    Info: Elapsed time: 00:00:12