dled.fit.eqn

使用VerilogHDL语言实现硬件的开发模拟

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--B1_dffs[0] is lpm_counter:count_rtl_0|dffs[0] at LC3
B1_dffs[0]_reg_input = VCC;
B1_dffs[0] = TFFE(B1_dffs[0]_reg_input, GLOBAL(clock), , , );


--B1_dffs[1] is lpm_counter:count_rtl_0|dffs[1] at LC4
B1_dffs[1]_or_out = B1_dffs[0];
B1_dffs[1]_reg_input = B1_dffs[1] $ B1_dffs[1]_or_out;
B1_dffs[1] = DFFE(B1_dffs[1]_reg_input, GLOBAL(clock), , , );


--B1_dffs[2] is lpm_counter:count_rtl_0|dffs[2] at LC5
B1_dffs[2]_p1_out = B1_dffs[1] & B1_dffs[0];
B1_dffs[2]_or_out = B1_dffs[2];
B1_dffs[2]_reg_input = B1_dffs[2]_p1_out $ B1_dffs[2]_or_out;
B1_dffs[2] = DFFE(B1_dffs[2]_reg_input, GLOBAL(clock), , , );


--B1_dffs[3] is lpm_counter:count_rtl_0|dffs[3] at LC6
B1_dffs[3]_p1_out = B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[3]_or_out = B1_dffs[3];
B1_dffs[3]_reg_input = B1_dffs[3]_p1_out $ B1_dffs[3]_or_out;
B1_dffs[3] = DFFE(B1_dffs[3]_reg_input, GLOBAL(clock), , , );


--B1_dffs[4] is lpm_counter:count_rtl_0|dffs[4] at LC7
B1_dffs[4]_p1_out = B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[4]_or_out = B1_dffs[4];
B1_dffs[4]_reg_input = B1_dffs[4]_p1_out $ B1_dffs[4]_or_out;
B1_dffs[4] = DFFE(B1_dffs[4]_reg_input, GLOBAL(clock), , , );


--B1_dffs[5] is lpm_counter:count_rtl_0|dffs[5] at LC8
B1_dffs[5]_p1_out = B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[5]_or_out = B1_dffs[5];
B1_dffs[5]_reg_input = B1_dffs[5]_p1_out $ B1_dffs[5]_or_out;
B1_dffs[5] = DFFE(B1_dffs[5]_reg_input, GLOBAL(clock), , , );


--B1_dffs[6] is lpm_counter:count_rtl_0|dffs[6] at LC9
B1_dffs[6]_p1_out = B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[6]_or_out = B1_dffs[6];
B1_dffs[6]_reg_input = B1_dffs[6]_p1_out $ B1_dffs[6]_or_out;
B1_dffs[6] = DFFE(B1_dffs[6]_reg_input, GLOBAL(clock), , , );


--B1_dffs[7] is lpm_counter:count_rtl_0|dffs[7] at LC10
B1_dffs[7]_p1_out = B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[7]_or_out = B1_dffs[7];
B1_dffs[7]_reg_input = B1_dffs[7]_p1_out $ B1_dffs[7]_or_out;
B1_dffs[7] = DFFE(B1_dffs[7]_reg_input, GLOBAL(clock), , , );


--B1_dffs[8] is lpm_counter:count_rtl_0|dffs[8] at LC11
B1_dffs[8]_p1_out = B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[8]_or_out = B1_dffs[8]_p1_out;
B1_dffs[8]_reg_input = B1_dffs[8]_or_out;
B1_dffs[8] = TFFE(B1_dffs[8]_reg_input, GLOBAL(clock), , , );


--B1_dffs[9] is lpm_counter:count_rtl_0|dffs[9] at LC12
B1_dffs[9]_p1_out = B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[9]_or_out = B1_dffs[9];
B1_dffs[9]_reg_input = B1_dffs[9]_p1_out $ B1_dffs[9]_or_out;
B1_dffs[9] = DFFE(B1_dffs[9]_reg_input, GLOBAL(clock), , , );


--B1_dffs[10] is lpm_counter:count_rtl_0|dffs[10] at LC13
B1_dffs[10]_p1_out = B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[10]_or_out = B1_dffs[10];
B1_dffs[10]_reg_input = B1_dffs[10]_p1_out $ B1_dffs[10]_or_out;
B1_dffs[10] = DFFE(B1_dffs[10]_reg_input, GLOBAL(clock), , , );


--B1_dffs[11] is lpm_counter:count_rtl_0|dffs[11] at LC14
B1_dffs[11]_p1_out = B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[11]_or_out = B1_dffs[11];
B1_dffs[11]_reg_input = B1_dffs[11]_p1_out $ B1_dffs[11]_or_out;
B1_dffs[11] = DFFE(B1_dffs[11]_reg_input, GLOBAL(clock), , , );


--B1_dffs[12] is lpm_counter:count_rtl_0|dffs[12] at LC15
B1_dffs[12]_p1_out = B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[12]_or_out = B1_dffs[12];
B1_dffs[12]_reg_input = B1_dffs[12]_p1_out $ B1_dffs[12]_or_out;
B1_dffs[12] = DFFE(B1_dffs[12]_reg_input, GLOBAL(clock), , , );


--B1_dffs[13] is lpm_counter:count_rtl_0|dffs[13] at LC2
B1_dffs[13]_p1_out = B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[13]_or_out = B1_dffs[13];
B1_dffs[13]_reg_input = B1_dffs[13]_p1_out $ B1_dffs[13]_or_out;
B1_dffs[13] = DFFE(B1_dffs[13]_reg_input, GLOBAL(clock), , , );


--B1_dffs[14] is lpm_counter:count_rtl_0|dffs[14] at LC1
B1_dffs[14]_p1_out = B1_dffs[13] & B1_dffs[12] & B1_dffs[11] & B1_dffs[10] & B1_dffs[9] & B1_dffs[8] & B1_dffs[7] & B1_dffs[6] & B1_dffs[5] & B1_dffs[4] & B1_dffs[3] & B1_dffs[2] & B1_dffs[1] & B1_dffs[0];
B1_dffs[14]_or_out = B1_dffs[14];
B1_dffs[14]_reg_input = B1_dffs[14]_p1_out $ B1_dffs[14]_or_out;
B1_dffs[14] = DFFE(B1_dffs[14]_reg_input, GLOBAL(clock), , , );


--A1L21 is reduce_or~23 at LC72
A1L21_p1_out = B1_dffs[14] & B1_dffs[13];
A1L21_or_out = A1L21_p1_out;
A1L21 = !(A1L21_or_out);


--A1L1 is Decoder~32 at LC77
A1L1_p1_out = !B1_dffs[14] & !B1_dffs[13];
A1L1_or_out = A1L1_p1_out;
A1L1 = !(A1L1_or_out);


--A1L2 is Decoder~36 at LC80
A1L2_p1_out = !B1_dffs[14] & B1_dffs[13];
A1L2_or_out = A1L2_p1_out;
A1L2 = !(A1L2_or_out);


--A1L3 is Decoder~39 at LC83
A1L3_p1_out = B1_dffs[14] & !B1_dffs[13];
A1L3_or_out = A1L3_p1_out;
A1L3 = !(A1L3_or_out);


--A1L31 is reduce_or~26 at LC67
A1L31_or_out = !B1_dffs[13];
A1L31 = B1_dffs[14] $ A1L31_or_out;


--A1L41 is reduce_or~32 at LC51
A1L41_p1_out = B1_dffs[14] & !B1_dffs[13];
A1L41_p2_out = !B1_dffs[14] & B1_dffs[13];
A1L41_or_out = A1L41_p1_out # A1L41_p2_out;
A1L41 = !(A1L41_or_out);


--A1L4 is Decoder~42 at LC65
A1L4_p1_out = !B1_dffs[14] & B1_dffs[13];
A1L4_or_out = A1L4_p1_out;
A1L4 = A1L4_or_out;


--A1L5 is Decoder~44 at LC69
A1L5_p1_out = !B1_dffs[14] & B1_dffs[13];
A1L5_or_out = A1L5_p1_out;
A1L5 = !(A1L5_or_out);


--A1L51 is reduce_or~34 at LC85
A1L51_p1_out = B1_dffs[14] & B1_dffs[13];
A1L51_or_out = A1L51_p1_out;
A1L51 = !(A1L51_or_out);


--A1L6 is Decoder~46 at LC73
A1L6_p1_out = !B1_dffs[14] & !B1_dffs[13];
A1L6_or_out = A1L6_p1_out;
A1L6 = A1L6_or_out;


--~GND~0 is ~GND~0 at LC49
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~VCC~0 is ~VCC~0 at LC75
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--clock is clock at PIN_83
--operation mode is input

clock = INPUT();


--seg[1] is seg[1] at PIN_41
--operation mode is output

seg[1] = OUTPUT(~GND~0);


--seg[7] is seg[7] at PIN_50
--operation mode is output

seg[7] = OUTPUT(~VCC~0);


--seg[3] is seg[3] at PIN_45
--operation mode is output

seg[3] = OUTPUT(A1L31);


--seg[5] is seg[5] at PIN_48
--operation mode is output

seg[5] = OUTPUT(A1L21);


--sl[0] is sl[0] at PIN_51
--operation mode is output

sl[0] = OUTPUT(A1L1);


--sl[1] is sl[1] at PIN_52
--operation mode is output

sl[1] = OUTPUT(A1L2);


--sl[2] is sl[2] at PIN_54
--operation mode is output

sl[2] = OUTPUT(A1L3);


--seg[0] is seg[0] at PIN_40
--operation mode is output

seg[0] = OUTPUT(A1L41);


--seg[2] is seg[2] at PIN_44
--operation mode is output

seg[2] = OUTPUT(A1L4);


--seg[4] is seg[4] at PIN_46
--operation mode is output

seg[4] = OUTPUT(A1L5);


--seg[6] is seg[6] at PIN_49
--operation mode is output

seg[6] = OUTPUT(A1L6);


--sl[3] is sl[3] at PIN_55
--operation mode is output

sl[3] = OUTPUT(A1L51);