dled.fit.rpt

来自「使用VerilogHDL语言实现硬件的开发模拟」· RPT 代码 · 共 457 行 · 第 1/5 页

; I/O Standard ; Load  ; Termination Resistance ;
+--------------+-------+------------------------+
; LVTTL        ; 10 pF ; Not Available          ;
; LVCMOS       ; 10 pF ; Not Available          ;
; TTL          ; 0 pF  ; Not Available          ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+----------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                            ;
+------------------------------+------------+------+-------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name           ;
+------------------------------+------------+------+-------------------------------+
; |dled                        ; 27         ; 17   ; |dled                         ;
;    |lpm_counter:count_rtl_0| ; 15         ; 0    ; |dled|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+-------------------------------+


+---------------------------------------------------------------------------------------+
; Control Signals                                                                       ;
+-------+----------+---------+-------+--------+----------------------+------------------+
; Name  ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+-------+--------+----------------------+------------------+
; clock ; PIN_83   ; 15      ; Clock ; yes    ; On                   ; --               ;
+-------+----------+---------+-------+--------+----------------------+------------------+


+----------------------------------------------------------------------+
; Global & Other Fast Signals                                          ;
+-------+----------+---------+----------------------+------------------+
; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+----------------------+------------------+
; clock ; PIN_83   ; 15      ; On                   ; --               ;
+-------+----------+---------+----------------------+------------------+


+--------------------------------------------+
; Non-Global High Fan-Out Signals            ;
+----------------------------------+---------+
; Name                             ; Fan-Out ;
+----------------------------------+---------+
; lpm_counter:count_rtl_0|dffs[1]  ; 14      ;
; lpm_counter:count_rtl_0|dffs[0]  ; 14      ;
; lpm_counter:count_rtl_0|dffs[2]  ; 13      ;
; lpm_counter:count_rtl_0|dffs[13] ; 12      ;
; lpm_counter:count_rtl_0|dffs[3]  ; 12      ;
; lpm_counter:count_rtl_0|dffs[14] ; 11      ;
; lpm_counter:count_rtl_0|dffs[4]  ; 11      ;
; lpm_counter:count_rtl_0|dffs[5]  ; 10      ;
; lpm_counter:count_rtl_0|dffs[6]  ; 9       ;
; lpm_counter:count_rtl_0|dffs[7]  ; 8       ;
; lpm_counter:count_rtl_0|dffs[9]  ; 6       ;
; lpm_counter:count_rtl_0|dffs[8]  ; 6       ;
; lpm_counter:count_rtl_0|dffs[10] ; 5       ;
; lpm_counter:count_rtl_0|dffs[11] ; 4       ;
; lpm_counter:count_rtl_0|dffs[12] ; 3       ;
; ~VCC~0                           ; 1       ;
; ~GND~0                           ; 1       ;
; Decoder~46                       ; 1       ;
; reduce_or~34                     ; 1       ;
; Decoder~44                       ; 1       ;
; Decoder~42                       ; 1       ;
; reduce_or~32                     ; 1       ;
; reduce_or~26                     ; 1       ;
; Decoder~39                       ; 1       ;
; Decoder~36                       ; 1       ;
; Decoder~32                       ; 1       ;
; reduce_or~23                     ; 1       ;
+----------------------------------+---------+


+-----------------------------------------------+
; Interconnect Usage Summary                    ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage            ;
+----------------------------+------------------+
; Output enables             ; 0 / 6 ( 0 % )    ;
; PIA buffers                ; 19 / 288 ( 6 % ) ;
; PIAs                       ; 21 / 288 ( 7 % ) ;
+----------------------------+------------------+


+----------------------------------------------------------------------------+
; LAB External Interconnect                                                  ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects  (Average = 2.63) ; Number of LABs  (Total = 4) ;
+----------------------------------------------+-----------------------------+
; 0                                            ; 4                           ;
; 1                                            ; 0                           ;
; 2                                            ; 3                           ;
; 3                                            ; 0                           ;