📄 init860.s
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#---------------------------------------------------
addi r3,r0,0x1E00
mtspr SPRG0,r3
#---------------------------------------------------------
# load link register in order to jump to physical address
#---------------------------------------------------------
addis r3,0,handler@h
ori r3,r3,handler@l
mtspr LR,r3
bclr 20,0 # jump unconditionally to address in Link
# Register (LR)
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# 1F00: IMPLEMENTATION-DEPENDENT NON-MASKABLE DEVELOPMENT PORT BREAKPOINT
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.skip 0x1F00-(.-VectorTable)
__Xnmdpbrk:
#-------------------------------------------#
# save off registers used in vector routine #
#-------------------------------------------#
mtspr SPRG3,r3 # save r3
mfspr r3,LR
mtspr SPRG2,r3 # save LR
#---------------------------------------------------
# Load the vector offset value in SPRG0 for handler
#---------------------------------------------------
addi r3,r0,0x1F00
mtspr SPRG0,r3
#---------------------------------------------------------
# load link register in order to jump to physical address
#---------------------------------------------------------
addis r3,0,handler@h
ori r3,r3,handler@l
mtspr LR,r3
bclr 20,0 # jump unconditionally to address in Link
# Register (LR)
VectorTableEnd:
#----------------------------------------------------------------------------
# This section defines exception jump points and functions that can be called
# by code outside this module.
#----------------------------------------------------------------------------
.globl VectorTable # Exception Vector Table label definition
.globl Xreset # Software Reset Exception jump point label
.globl _start # Label where first instruction gets executed
.globl _longjump # jump label
.globl exit # infinite loop label
.globl init_stack # function that initializes the stack
.globl flush_cache # function that flushes the entire cache
.globl main # main function
#----------------------------------------------------------------------------
# On-Chip Core Registers. These values represent the special purpose
# registers used in this example. Refer to PowerPC Microprocessor Family:
# The Programming Environments for 32-Bit Microprocessors book for the
# complete set and the MPC860 Users Manual.
#----------------------------------------------------------------------------
LR: .equ 8 # Link register
CTR: .equ 9 # Counter register
SRR0: .equ 26 # Save/Restore Register 0
SRR1: .equ 27 # Save/Restore Register 1
ICR: .equ 148 # Interrupt Cause Register
ICTRL: .equ 158 # Instruction Control Register
DER: .equ 149 # Debug Enable Register
DPDR: .equ 630 # Development Port Data Register
IMMR: .equ 638 # Internal I/O base register
IC_CST: .equ 560 # ICache Control Status Register
IC_ADR: .equ 561 # ICache Address Register
IC_DAT: .equ 562 # ICache Data Register
DC_CST: .equ 568 # DCache Control Status Register
DC_ADR: .equ 569 # DCache Address Register
DC_DAT: .equ 570 # DCache Data Register
MI_CTR: .equ 784 # MMU Instrction Control Register
MD_CTR: .equ 792 # MMU Data Control Register
MD_AP: .equ 794 # MMU Data Access Permission Register
MD_EPN: .equ 795 # MMU Data Effective Page Number Register
MD_TWC: .equ 797 # MMU Data Tablewalk Control Register
MD_RPN: .equ 798 # MMU Instruction Real Page Number Register
MI_AP: .equ 786 # MMU Instruction Access Permission Register
MI_EPN: .equ 787 # MMU Instruction Effective Page Number Reg
MI_TWC: .equ 789 # MMU Instruction Tablewalk Control Register
MI_RPN: .equ 790 # MMU Instruction Real Page Number Register
#----------------------------------------------------------------------------
# Register Offset Definitions. All these values are offsets from the
# Internal Memory Map Register (IMMR) base pointer. The base value is deter-
# mined by the ISB bits in the Hard Reset Configuration Word. This word is
# read on the data bus or is a default of 0. See the reset section of the
# user's manual. For a complete set of all the IMMR registers, refer to the
# MPC860 Users Manual.
#----------------------------------------------------------------------------
SIUMCR: .equ 0x000 # SIU Module configuration
SYPCR: .equ 0x004 # SIU System Protection Control
BR0: .equ 0x100 # Base Register 0
OR0: .equ 0x104 # Option Register 0
BR1: .equ 0x108 # Base Register 1
OR1: .equ 0x10C # Option Register 1
BR2: .equ 0x110 # Base Register 2
OR2: .equ 0x114 # Option Register 2
MCR: .equ 0x168 # Memory Command
MAMR: .equ 0x170 # Machine A Mode Register
MPTPR: .equ 0x17A # Memory Periodic Timer Prescaler
MDR: .equ 0x17C # Memory Data
TBSCR: .equ 0x200 # Time Base Status and Control Register
RTCSC: .equ 0x220 # Real Timer Clock Status and Control
PISCR: .equ 0x240 # PIT Status and Control
SCCR: .equ 0x280 # System Clock Control Register
PLPRCR: .equ 0x284 # PLL, Low power & Reset Control Register
#----------------------------------------
# Instruction and Data Cache definition.
# Note: must load into bits 0-15
#----------------------------------------
CacheUnlockAllCmd: .equ 0x0A00 # Cache Unlock_All command
CacheDisableCmd: .equ 0x0400 # Cache Disable command
CacheInvAllCmd: .equ 0x0C00 # Cache Invalidate_All command
CacheEnableCmd: .equ 0x0200 # DCache_Enable Command
CacheEnableBit: .equ 0x8000 # Cache Enable bit in I/DC_CST
#---------------------------------
# Interrupt StackFrame Definitions
#---------------------------------
R0_OFFSET: .equ (0*4) # R0 Stack Offset
R1_OFFSET: .equ (1*4) # R1 Stack Offset
R2_OFFSET: .equ (2*4) # R2 Stack Offset
R3_OFFSET: .equ (3*4) # R3 Stack Offset
R4_OFFSET: .equ (4*4) # R4 Stack Offset
R5_OFFSET: .equ (5*4) # R5 Stack Offset
R6_OFFSET: .equ (6*4) # R6 Stack Offset
R7_OFFSET: .equ (7*4) # R7 Stack Offset
R8_OFFSET: .equ (8*4) # R8 Stack Offset
R9_OFFSET: .equ (9*4) # R9 Stack Offset
R10_OFFSET: .equ (10*4) # R10 Stack Offset
R11_OFFSET: .equ (11*4) # R11 Stack Offset
R12_OFFSET: .equ (12*4) # R12 Stack Offset
SRR0_OFFSET: .equ (13*4) # SRR0 Stack Offset
SRR1_OFFSET: .equ (14*4) # SRR1 Stack Offset
LR_OFFSET: .equ (15*4) # LR Stack Offset
CTR_OFFSET: .equ (16*4) # CTR Stack Offset
XER_OFFSET: .equ (17*4) # XER Stack Offset
CR_OFFSET: .equ (18*4) # CR Stack Offset
STACK_SZ: .equ (20*4) # Quad-Word Aligned Interrupt Stack Frame
C_FRAME_SZ: .equ (4*4) # Quad-Word Aligned C Frame Size
#########################################################################
# Tables Section
#########################################################################
#-------------------------------------------------------------------------
# UPM contents for the default MPC 860 ADS memory configuration. This
# example configures for (2) 1 Mbyte x 16 Fast Page Mode DRAMs ganged
# together to form a 1 Mbyte x 32 memory bank which has a 1024 cycle
# refresh. The access time is 60 ns.
#-------------------------------------------------------------------------
UpmTable:
#-----------------
# UPM A contents:
#-----------------
#----------------------------------------------------
# Read Single Beat Cycle. Offset 0 in the RAM array.
#----------------------------------------------------
.4byte 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04
.4byte 0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff
#------------------------------------------------
# Read Burst Cycle. Offset 0x8 in the RAM array.
#------------------------------------------------
.4byte 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c
.4byte 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44
.4byte 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00
.4byte 0x3fffc847, 0x3fffec47, 0xffffffff, 0xffffffff
#-------------------------------------------------------
# Write Single Beat Cycle. Offset 0x18 in the RAM array
#-------------------------------------------------------
.4byte 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47
.4byte 0xc0ffcc84, 0xffffffff, 0xffffffff, 0xffffffff
#-------------------------------------------------
# Write Burst Cycle. Offset 0x20 in the RAM array
#-------------------------------------------------
.4byte 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c
.4byte 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c
.4byte 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff
.4byte 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
#------------------------------------------------------------------------
# Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
#------------------------------------------------------------------------
.4byte 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06
.4byte 0xffffcc85, 0xffffcc05, 0xffffcc05, 0xffffffff
.4byte 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
#-----------
# Exception:
#-----------
.4byte 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff
UpmTableEnd:
#########################################################################
# Function: start
#
# Description: This is the main startup function
#
# History:
#
# 2/23/98 jay
#
#########################################################################
_start:
#-------------------------------------------------------------------------
# When the MPC860 comes out of reset, the BCSR0 (Board Control and Status
# Register) drives the data bus with 0x41600000. This becomes the Hard
# Reset Configuration Word (HRCW). The IP bit in the HRCW is set so the
# reset exception Vector location is 0x00000100. This method of driving
# the bus is one of two ways to program the HRCW. The other is to accept
# the internal MPC860 default value. The details are explained in the
# reset section in the users manual. The flash on my development board is
# 512K by 32 bits wide. CS0 is tied directly to the flash so CS0 is
# active for all addresses at reset. The vector table is re-located from
# flash to physical address 0x00000000 in DRAM once chip selects are
# defined later in this initialization code.
#-------------------------------------------------------------------------
#-------------------------------------------------------------------------
# Re-program the Machine State Register (MSR). Re-program the MSR(IP)
# bit to ensure the vector interrupt table starts at 0x00000000 for all
# exceptions that occur after the vector table is relocated to 0x00000000
# further down in this code. The Machine Check Exception is enabled
# and The RI bit which makes exceptions recoverable.
#-------------------------------------------------------------------------
addis r0,0,0 # load r0 with 0. This register will always be 0
# in this module.
ori r3,r0,0x1002 # Set ME,RI flags
mtmsr r3
mtspr SRR1,r3 # Need SRR1 to match MSR
#-------------------------------------------------------------------------
# Load the following physical address into the Link Register. Jump to that
# address so that LR equals Program Counter (PC).
#-------------------------------------------------------------------------
oris r3,r0,_sync_jump@h # load the address
ori r3,r3,_sync_jump@l
mtspr LR,r3
bclr 20,0 # jump unconditionally to address in Link
# Register (LR)
_sync_jump:
#-------------------------------------------------------------------------
# Invalidate all TLB entries: This needs to be done because Translation
# Lookaside Buffers values are undefined. The MMU comes out of reset
# disabled but if the MMU were enabled and TLB's were not invalidated
# first, erratic behavior would result.
#-------------------------------------------------------------------------
tlbia # This single command invalidates all TLB entries
isync # This ensures that no other instruction is fetched until tlbia is
# completely finished
##############################################
# Call 8xx_init to finish chip initialization.
##############################################
bl mpc8xx_init # User specific init code
#############################################################
# Initialize the stack for the main program's code execution
#############################################################
bl init_stack # INIT THE STACK
###########################################################
# Jump to main(). There shouldn't be a return from main().
###########################################################
bl main # JUMP TO MAIN()
exit:
b exit # If there is a return from main(), loop forever
#########################################################################
# Function: 8xx_init
#
# Description: This function initializes the rest of the 8xx with the
# exception of the CPM.
#
# History:
#
# 4/28/98 jay
#
#########################################################################
mpc8xx_init:
mfspr r31,LR # Save the Link Register value
#-----------------------------------------------------------------------
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