s3c2410_dma_3.h

自己写的支持S3C2410下的实时DMA操作的linux平台驱动程序 功能完善

/******************************************************************************************************/
#ifndef S3C2410_DMA_H
#define S3C2410_DMA_H
/*
	Head file for s3c2410_dma.h
*/
#ifdef __KERNEL__
#include <linux/spinlock.h>
#include <asm/dma.h>
#include <linux/wait.h>

#define DEVICE_NAME 	"s3c2410DMA-DRIVER"
#define HWFIFOSIZE 		(512>>1)			//Half Fifo	256	
#define FIFOSIZE 		((HWFIFOSIZE)*sizeof(int))//1024
#define S3C2410_DMA_NUMSBUF	8

#define DMA_TRANS_NUM 	((HWFIFOSIZE)>>2) //  //4--DSZ
#define DMA_BUF_WR0 0
#define DMA_BUF_WR1 1
#define DMA_CHECK 5
#define DMA_DSTAT0 6
#define DMA_CHECK_ON 7
#define DMA_SET_STOP 8
#define DMA_SET_READ 9
#define HARDWARE_FIFO_ADDR 0x28000000
#ifdef PAGESIZE
#undef PAGESIZE
#endif
#define PAGESIZE (1<<12)// 4k
//#define rSRCPND     (*(volatile unsigned *)0x4a000000) //Interrupt request status
//#define rINTPND     (*(volatile unsigned *)0x4a000010) //Interrupt request status

static devfs_handle_t devfs_handle;
//static char * fifo_start = (char *)io_p2v(HARDWARE_FIFO_ADDR);
static char * fifo_check_rd = NULL;//=(char *) io_p2v(HARDWARE_FIFO_CHECK_READ);
static  char * fifo_check_wr = NULL;//= (char *)io_p2v(HARDWARE_FIFO_CHECK_WRITE);

typedef struct
{
	int size;		/* buffer size */
	int valid_size;
	int num;
	int active[2];
	char *start;
	char *curr_pos;
} user_buf_t;
static user_buf_t usr_buff_write;
//user_buf_t *usr_buff_write1 = NULL;
typedef struct
{
	int size;		/* buffer size */
	char *start;		/* point to actual buffer */
	char *user_space;
	int write_or_rd;
	int size_valid;
	dma_addr_t dma_addr;	/* physical buffer address */
	struct semaphore sem;	/* down before touching the buffer */
	dmach_t dma_ch; /* DMA channel*/
	int dirty;
	//int user_buff_num;
} dma_buf_t;

static dma_buf_t s3c2410_dmabuffer_array_rd[S3C2410_DMA_NUMSBUF];
static dma_buf_t s3c2410_dmabuffer_array_wr;// 1k
static dma_buf_t s3c2410_dma_buff_rd;
static dma_buf_t  dma_buff_temp_2page;
static dma_buf_t dma_buff_cur_int;
int ch0_buff_rd  = 0;


//dma_buf_t * dma_buff_fifo = NULL;
/**/
typedef struct {
	volatile u_long DISRC;
	volatile u_long DISRCC;
	volatile u_long DIDST;
	volatile u_long DIDSTC;
	volatile u_long DCON;
	volatile u_long DSTAT;
	volatile u_long DCSRC;
	volatile u_long DCDST;
	volatile u_long DMASKTRIG;
} dma_regs_t;
struct semaphore dma0_sem;	
//struct semaphore sem_mmap;
//struct semaphore protect_write_sem;
spinlock_t protect_dma_lock = SPIN_LOCK_UNLOCKED;
//wait_queue_head_t wq ;

static dma_regs_t *dma_types[2];
/**/
/*
******************************************************************************************************/
/*DMA0 Controler Configuation*/
#ifdef BUF_ON_AHB
#undef BUF_ON_AHB
#endif
#ifdef BUF_ON_MEM 
#undef BUF_ON_MEM
#endif
/***********************************************************/
#define BUF_ON_MEM		(ON_AHB | ADDR_INC)
#define BUF_ON_AHB		(ON_AHB	| ADDR_FIX)//Addrase Fix
#define  rXDREQ0_WR_CTL_1	(HS_MODE | SYNC_HCLK | INT_MODE | TSZ_BURST )
#define rXDREQ0_WR_CTL_2   (WHOLE_SERVICE | HWSRC(CH0_nXDREQ0) | DMA_SRC_HW )
#define   rXDREQ0_WR_CTL_3     ( SET_ATRELOAD | DSZ(DSZ_WORD) | TX_CNT(0))
//#define rXDREQ0_RD_SRC			DMA_UNDEF
//#define rXDREQ0_RD_DST(y)		DMA_UNDEF
#define rXDREQ0_WR_CTL (rXDREQ0_WR_CTL_1|rXDREQ0_WR_CTL_2|rXDREQ0_WR_CTL_3)
#define rXDREQ0_WR_SRC_CTL	BUF_ON_MEM//BUF_ON_APB
#define rXDREQ0_WR_DST_CTL	BUF_ON_AHB
//write control
#define rXDREQ0_RD_CTL_a	(HS_MODE | SYNC_HCLK | INT_MODE | TSZ_BURST )
#define rXDREQ0_RD_CTL_b     (WHOLE_SERVICE | HWSRC(CH0_nXDREQ0) | DMA_SRC_HW )
#define rXDREQ0_RD_CTL_c     ( SET_ATRELOAD | DSZ(DSZ_WORD) | TX_CNT(0))
#define rXDREQ0_RD_CTL        (rXDREQ0_RD_CTL_a|rXDREQ0_RD_CTL_b|rXDREQ0_RD_CTL_c)
#define rXDREQ0_RD_SRC_CTL	BUF_ON_AHB		
#define rXDREQ0_RD_DST_CTL	BUF_ON_MEM//BUF_ON_APB

/*
#define rXDREQ0_WR_SRC_CTL	BUF_ON_MEM//BUF_ON_APB
#define rXDREQ0_WR_DST_CTL	BUF_ON_APB
#define rXDREQ0_RD_SRC_CTL	BUF_ON_APB		
#define rXDREQ0_RD_DST_CTL	BUF_ON_MEM//BUF_ON_APB
rXDREQ0_RD_CTL |= 
*/
/******************************************************************************************************/

#endif
#endif