cpu.hier_info

CPU 的简单功能的模拟

|cpu
reset => Write_Read~0.IN0
reset => status[2].ACLR
reset => status[1].ACLR
reset => MDR[6].ACLR
reset => MDR[5].ACLR
reset => MDR[4].ACLR
reset => MDR[3].ACLR
reset => MDR[2].ACLR
reset => MDR[1].ACLR
reset => MDR[0].ACLR
reset => status[0].ACLR
reset => MDR[7].ACLR
reset => MAR[0].ACLR
reset => MAR[1].ACLR
reset => MAR[2].ACLR
reset => MAR[3].ACLR
reset => MAR[4].ACLR
reset => MAR[5].ACLR
reset => MAR[6].ACLR
reset => MAR[7].ACLR
reset => MAR[8].ACLR
reset => MAR[9].ACLR
reset => MAR[10].ACLR
reset => MAR[11].ACLR
reset => IR[0].ACLR
reset => IR[1].ACLR
reset => IR[2].ACLR
reset => IR[3].ACLR
reset => IR[4].ACLR
reset => IR[5].ACLR
reset => IR[6].ACLR
reset => IR[7].ACLR
reset => IR[8].ACLR
reset => IR[9].ACLR
reset => IR[10].ACLR
reset => IR[11].ACLR
reset => IR[12].ACLR
reset => IR[13].ACLR
reset => IR[14].ACLR
reset => IR[15].ACLR
reset => \seq:A[0].ACLR
reset => \seq:A[1].ACLR
reset => \seq:A[2].ACLR
reset => \seq:A[3].ACLR
reset => \seq:A[4].ACLR
reset => \seq:A[5].ACLR
reset => \seq:A[6].ACLR
reset => \seq:A[7].ACLR
reset => \seq:R3[0].ACLR
reset => \seq:R3[1].ACLR
reset => \seq:R3[2].ACLR
reset => \seq:R3[3].ACLR
reset => \seq:R3[4].ACLR
reset => \seq:R3[5].ACLR
reset => \seq:R3[6].ACLR
reset => \seq:R3[7].ACLR
reset => \seq:R2[0].ACLR
reset => \seq:R2[1].ACLR
reset => \seq:R2[2].ACLR
reset => \seq:R2[3].ACLR
reset => \seq:R2[4].ACLR
reset => \seq:R2[5].ACLR
reset => \seq:R2[6].ACLR
reset => \seq:R2[7].ACLR
reset => \seq:R1[0].ACLR
reset => \seq:R1[1].ACLR
reset => \seq:R1[2].ACLR
reset => \seq:R1[3].ACLR
reset => \seq:R1[4].ACLR
reset => \seq:R1[5].ACLR
reset => \seq:R1[6].ACLR
reset => \seq:R1[7].ACLR
reset => \seq:R0[0].ACLR
reset => \seq:R0[1].ACLR
reset => \seq:R0[2].ACLR
reset => \seq:R0[3].ACLR
reset => \seq:R0[4].ACLR
reset => \seq:R0[5].ACLR
reset => \seq:R0[6].ACLR
reset => \seq:R0[7].ACLR
reset => \seq:PC[0].ACLR
reset => \seq:PC[1].ACLR
reset => \seq:PC[2].ACLR
reset => \seq:PC[3].ACLR
reset => \seq:PC[4].ACLR
reset => \seq:PC[5].ACLR
reset => \seq:PC[6].ACLR
reset => \seq:PC[7].ACLR
reset => \seq:PC[8].ACLR
reset => \seq:PC[9].ACLR
reset => \seq:PC[10].ACLR
reset => \seq:PC[11].ACLR
reset => overflow~reg0.ENA
clock => overflow~reg0.CLK
clock => MDR[0].CLK
clock => MDR[1].CLK
clock => MDR[2].CLK
clock => MDR[3].CLK
clock => MDR[4].CLK
clock => MDR[5].CLK
clock => MDR[6].CLK
clock => MDR[7].CLK
clock => MAR[0].CLK
clock => MAR[1].CLK
clock => MAR[2].CLK
clock => MAR[3].CLK
clock => MAR[4].CLK
clock => MAR[5].CLK
clock => MAR[6].CLK
clock => MAR[7].CLK
clock => MAR[8].CLK
clock => MAR[9].CLK
clock => MAR[10].CLK
clock => MAR[11].CLK
clock => IR[0].CLK
clock => IR[1].CLK
clock => IR[2].CLK
clock => IR[3].CLK
clock => IR[4].CLK
clock => IR[5].CLK
clock => IR[6].CLK
clock => IR[7].CLK
clock => IR[8].CLK
clock => IR[9].CLK
clock => IR[10].CLK
clock => IR[11].CLK
clock => IR[12].CLK
clock => IR[13].CLK
clock => IR[14].CLK
clock => IR[15].CLK
clock => \seq:A[0].CLK
clock => \seq:A[1].CLK
clock => \seq:A[2].CLK
clock => \seq:A[3].CLK
clock => \seq:A[4].CLK
clock => \seq:A[5].CLK
clock => \seq:A[6].CLK
clock => \seq:A[7].CLK
clock => \seq:R3[0].CLK
clock => \seq:R3[1].CLK
clock => \seq:R3[2].CLK
clock => \seq:R3[3].CLK
clock => \seq:R3[4].CLK
clock => \seq:R3[5].CLK
clock => \seq:R3[6].CLK
clock => \seq:R3[7].CLK
clock => \seq:R2[0].CLK
clock => \seq:R2[1].CLK
clock => \seq:R2[2].CLK
clock => \seq:R2[3].CLK
clock => \seq:R2[4].CLK
clock => \seq:R2[5].CLK
clock => \seq:R2[6].CLK
clock => \seq:R2[7].CLK
clock => \seq:R1[0].CLK
clock => \seq:R1[1].CLK
clock => \seq:R1[2].CLK
clock => \seq:R1[3].CLK
clock => \seq:R1[4].CLK
clock => \seq:R1[5].CLK
clock => \seq:R1[6].CLK
clock => \seq:R1[7].CLK
clock => \seq:R0[0].CLK
clock => \seq:R0[1].CLK
clock => \seq:R0[2].CLK
clock => \seq:R0[3].CLK
clock => \seq:R0[4].CLK
clock => \seq:R0[5].CLK
clock => \seq:R0[6].CLK
clock => \seq:R0[7].CLK
clock => \seq:PC[0].CLK
clock => \seq:PC[1].CLK
clock => \seq:PC[2].CLK
clock => \seq:PC[3].CLK
clock => \seq:PC[4].CLK
clock => \seq:PC[5].CLK
clock => \seq:PC[6].CLK
clock => \seq:PC[7].CLK
clock => \seq:PC[8].CLK
clock => \seq:PC[9].CLK
clock => \seq:PC[10].CLK
clock => \seq:PC[11].CLK
clock => status[0].CLK
clock => status[1].CLK
clock => status[2].CLK
Write_Read <= Write_Read~1.DB_MAX_OUTPUT_PORT_TYPE
M_address[0] <= MAR[0].DB_MAX_OUTPUT_PORT_TYPE
M_address[1] <= MAR[1].DB_MAX_OUTPUT_PORT_TYPE
M_address[2] <= MAR[2].DB_MAX_OUTPUT_PORT_TYPE
M_address[3] <= MAR[3].DB_MAX_OUTPUT_PORT_TYPE
M_address[4] <= MAR[4].DB_MAX_OUTPUT_PORT_TYPE
M_address[5] <= MAR[5].DB_MAX_OUTPUT_PORT_TYPE
M_address[6] <= MAR[6].DB_MAX_OUTPUT_PORT_TYPE
M_address[7] <= MAR[7].DB_MAX_OUTPUT_PORT_TYPE
M_address[8] <= MAR[8].DB_MAX_OUTPUT_PORT_TYPE
M_address[9] <= MAR[9].DB_MAX_OUTPUT_PORT_TYPE
M_address[10] <= MAR[10].DB_MAX_OUTPUT_PORT_TYPE
M_address[11] <= MAR[11].DB_MAX_OUTPUT_PORT_TYPE
M_data_in[0] => Mux447.IN0
M_data_in[0] => Mux447.IN1
M_data_in[0] => Mux447.IN2
M_data_in[0] => Mux447.IN3
M_data_in[0] => Mux499.IN0
M_data_in[0] => Mux507.IN1
M_data_in[1] => Mux446.IN0
M_data_in[1] => Mux446.IN1
M_data_in[1] => Mux446.IN2
M_data_in[1] => Mux446.IN3
M_data_in[1] => Mux498.IN0
M_data_in[1] => Mux506.IN1
M_data_in[2] => Mux445.IN0
M_data_in[2] => Mux445.IN1
M_data_in[2] => Mux445.IN2
M_data_in[2] => Mux445.IN3
M_data_in[2] => Mux497.IN0
M_data_in[2] => Mux505.IN1
M_data_in[3] => Mux444.IN0
M_data_in[3] => Mux444.IN1
M_data_in[3] => Mux444.IN2
M_data_in[3] => Mux444.IN3
M_data_in[3] => Mux496.IN0
M_data_in[3] => Mux504.IN1
M_data_in[4] => Mux443.IN0
M_data_in[4] => Mux443.IN1
M_data_in[4] => Mux443.IN2
M_data_in[4] => Mux443.IN3
M_data_in[4] => Mux495.IN0
M_data_in[4] => Mux503.IN1
M_data_in[5] => Mux442.IN0
M_data_in[5] => Mux442.IN1
M_data_in[5] => Mux442.IN2
M_data_in[5] => Mux442.IN3
M_data_in[5] => Mux494.IN0
M_data_in[5] => Mux502.IN1
M_data_in[6] => Mux441.IN0
M_data_in[6] => Mux441.IN1
M_data_in[6] => Mux441.IN2
M_data_in[6] => Mux441.IN3
M_data_in[6] => Mux493.IN0
M_data_in[6] => Mux501.IN1
M_data_in[7] => Mux440.IN0
M_data_in[7] => Mux440.IN1
M_data_in[7] => Mux440.IN2
M_data_in[7] => Mux440.IN3
M_data_in[7] => Mux492.IN0
M_data_in[7] => Mux500.IN1
M_data_out[0] <= MDR[0].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[1] <= MDR[1].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[2] <= MDR[2].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[3] <= MDR[3].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[4] <= MDR[4].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[5] <= MDR[5].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[6] <= MDR[6].DB_MAX_OUTPUT_PORT_TYPE
M_data_out[7] <= MDR[7].DB_MAX_OUTPUT_PORT_TYPE
overflow <= overflow~reg0.DB_MAX_OUTPUT_PORT_TYPE