cpu.tan.qmsg

CPU 的简单功能的模拟

{ "Info" "ITDB_TH_RESULT" "overflow~reg0 reset clock -0.362 ns register " "Info: th for register \"overflow~reg0\" (data pin = \"reset\", clock pin = \"clock\") is -0.362 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.011 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.011 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 92 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 92; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.542 ns) 3.011 ns overflow~reg0 2 REG LC_X17_Y13_N1 1 " "Info: 2: + IC(1.641 ns) + CELL(0.542 ns) = 3.011 ns; Loc. = LC_X17_Y13_N1; Fanout = 1; REG Node = 'overflow~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.183 ns" { clock overflow~reg0 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.50 % ) " "Info: Total cell delay = 1.370 ns ( 45.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 54.50 % ) " "Info: Total interconnect delay = 1.641 ns ( 54.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.011 ns" { clock overflow~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.011 ns" { clock clock~out0 overflow~reg0 } { 0.000ns 0.000ns 1.641ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.473 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns reset 1 PIN PIN_M21 93 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 93; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.043 ns) + CELL(0.705 ns) 3.473 ns overflow~reg0 2 REG LC_X17_Y13_N1 1 " "Info: 2: + IC(2.043 ns) + CELL(0.705 ns) = 3.473 ns; Loc. = LC_X17_Y13_N1; Fanout = 1; REG Node = 'overflow~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { reset overflow~reg0 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.430 ns ( 41.17 % ) " "Info: Total cell delay = 1.430 ns ( 41.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.043 ns ( 58.83 % ) " "Info: Total interconnect delay = 2.043 ns ( 58.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.473 ns" { reset overflow~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.473 ns" { reset reset~out0 overflow~reg0 } { 0.000ns 0.000ns 2.043ns } { 0.000ns 0.725ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.011 ns" { clock overflow~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.011 ns" { clock clock~out0 overflow~reg0 } { 0.000ns 0.000ns 1.641ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.473 ns" { reset overflow~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.473 ns" { reset reset~out0 overflow~reg0 } { 0.000ns 0.000ns 2.043ns } { 0.000ns 0.725ns 0.705ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 19:56:09 2007 " "Info: Processing ended: Wed Nov 21 19:56:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}