cpu.tan.qmsg

CPU 的简单功能的模拟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register IR\[13\] register status\[1\] 113.38 MHz 8.82 ns Internal " "Info: Clock \"clock\" has Internal fmax of 113.38 MHz between source register \"IR\[13\]\" and destination register \"status\[1\]\" (period= 8.82 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.244 ns + Longest register register " "Info: + Longest register to register delay is 4.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IR\[13\] 1 REG LC_X12_Y14_N6 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y14_N6; Fanout = 49; REG Node = 'IR\[13\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { IR[13] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.411 ns) + CELL(0.183 ns) 1.594 ns IR\[13\]~1516 2 COMB LC_X17_Y13_N8 3 " "Info: 2: + IC(1.411 ns) + CELL(0.183 ns) = 1.594 ns; Loc. = LC_X17_Y13_N8; Fanout = 3; COMB Node = 'IR\[13\]~1516'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.594 ns" { IR[13] IR[13]~1516 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.388 ns) + CELL(0.183 ns) 3.165 ns Mux3~254 3 COMB LC_X8_Y14_N8 1 " "Info: 3: + IC(1.388 ns) + CELL(0.183 ns) = 3.165 ns; Loc. = LC_X8_Y14_N8; Fanout = 1; COMB Node = 'Mux3~254'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.571 ns" { IR[13]~1516 Mux3~254 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.223 ns) 4.244 ns status\[1\] 4 REG LC_X13_Y14_N8 40 " "Info: 4: + IC(0.856 ns) + CELL(0.223 ns) = 4.244 ns; Loc. = LC_X13_Y14_N8; Fanout = 40; REG Node = 'status\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.079 ns" { Mux3~254 status[1] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.589 ns ( 13.88 % ) " "Info: Total cell delay = 0.589 ns ( 13.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.655 ns ( 86.12 % ) " "Info: Total interconnect delay = 3.655 ns ( 86.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.244 ns" { IR[13] IR[13]~1516 Mux3~254 status[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.244 ns" { IR[13] IR[13]~1516 Mux3~254 status[1] } { 0.000ns 1.411ns 1.388ns 0.856ns } { 0.000ns 0.183ns 0.183ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.046 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 92 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 92; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.542 ns) 3.046 ns status\[1\] 2 REG LC_X13_Y14_N8 40 " "Info: 2: + IC(1.676 ns) + CELL(0.542 ns) = 3.046 ns; Loc. = LC_X13_Y14_N8; Fanout = 40; REG Node = 'status\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { clock status[1] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.98 % ) " "Info: Total cell delay = 1.370 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.676 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock status[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 status[1] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.046 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 92 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 92; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.542 ns) 3.046 ns IR\[13\] 2 REG LC_X12_Y14_N6 49 " "Info: 2: + IC(1.676 ns) + CELL(0.542 ns) = 3.046 ns; Loc. = LC_X12_Y14_N6; Fanout = 49; REG Node = 'IR\[13\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { clock IR[13] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.98 % ) " "Info: Total cell delay = 1.370 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.676 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock IR[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 IR[13] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock status[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 status[1] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock IR[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 IR[13] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 52 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.244 ns" { IR[13] IR[13]~1516 Mux3~254 status[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.244 ns" { IR[13] IR[13]~1516 Mux3~254 status[1] } { 0.000ns 1.411ns 1.388ns 0.856ns } { 0.000ns 0.183ns 0.183ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock status[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 status[1] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock IR[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 IR[13] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "\\seq:R0\[7\] M_data_in\[7\] clock 4.110 ns register " "Info: tsu for register \"\\seq:R0\[7\]\" (data pin = \"M_data_in\[7\]\", clock pin = \"clock\") is 4.110 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.115 ns + Longest pin register " "Info: + Longest pin to register delay is 7.115 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns M_data_in\[7\] 1 PIN PIN_U14 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U14; Fanout = 3; PIN Node = 'M_data_in\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { M_data_in[7] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.035 ns) + CELL(0.075 ns) 5.197 ns \\seq:R0\[0\]~2426 2 COMB LC_X18_Y16_N2 1 " "Info: 2: + IC(4.035 ns) + CELL(0.075 ns) = 5.197 ns; Loc. = LC_X18_Y16_N2; Fanout = 1; COMB Node = '\\seq:R0\[0\]~2426'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.110 ns" { M_data_in[7] \seq:R0[0]~2426 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.366 ns) 6.567 ns \\seq:R0\[0\]~2431 3 COMB LC_X19_Y14_N6 1 " "Info: 3: + IC(1.004 ns) + CELL(0.366 ns) = 6.567 ns; Loc. = LC_X19_Y14_N6; Fanout = 1; COMB Node = '\\seq:R0\[0\]~2431'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.370 ns" { \seq:R0[0]~2426 \seq:R0[0]~2431 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.223 ns) 7.115 ns \\seq:R0\[7\] 4 REG LC_X19_Y14_N0 23 " "Info: 4: + IC(0.325 ns) + CELL(0.223 ns) = 7.115 ns; Loc. = LC_X19_Y14_N0; Fanout = 23; REG Node = '\\seq:R0\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.548 ns" { \seq:R0[0]~2431 \seq:R0[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.751 ns ( 24.61 % ) " "Info: Total cell delay = 1.751 ns ( 24.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.364 ns ( 75.39 % ) " "Info: Total interconnect delay = 5.364 ns ( 75.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.115 ns" { M_data_in[7] \seq:R0[0]~2426 \seq:R0[0]~2431 \seq:R0[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.115 ns" { M_data_in[7] M_data_in[7]~out0 \seq:R0[0]~2426 \seq:R0[0]~2431 \seq:R0[7] } { 0.000ns 0.000ns 4.035ns 1.004ns 0.325ns } { 0.000ns 1.087ns 0.075ns 0.366ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.015 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 92 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 92; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.645 ns) + CELL(0.542 ns) 3.015 ns \\seq:R0\[7\] 2 REG LC_X19_Y14_N0 23 " "Info: 2: + IC(1.645 ns) + CELL(0.542 ns) = 3.015 ns; Loc. = LC_X19_Y14_N0; Fanout = 23; REG Node = '\\seq:R0\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.187 ns" { clock \seq:R0[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.44 % ) " "Info: Total cell delay = 1.370 ns ( 45.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.645 ns ( 54.56 % ) " "Info: Total interconnect delay = 1.645 ns ( 54.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.015 ns" { clock \seq:R0[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.015 ns" { clock clock~out0 \seq:R0[7] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.115 ns" { M_data_in[7] \seq:R0[0]~2426 \seq:R0[0]~2431 \seq:R0[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.115 ns" { M_data_in[7] M_data_in[7]~out0 \seq:R0[0]~2426 \seq:R0[0]~2431 \seq:R0[7] } { 0.000ns 0.000ns 4.035ns 1.004ns 0.325ns } { 0.000ns 1.087ns 0.075ns 0.366ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.015 ns" { clock \seq:R0[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.015 ns" { clock clock~out0 \seq:R0[7] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock Write_Read IR\[15\] 12.928 ns register " "Info: tco from clock \"clock\" to destination pin \"Write_Read\" through register \"IR\[15\]\" is 12.928 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.046 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 92 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 92; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.542 ns) 3.046 ns IR\[15\] 2 REG LC_X12_Y14_N3 57 " "Info: 2: + IC(1.676 ns) + CELL(0.542 ns) = 3.046 ns; Loc. = LC_X12_Y14_N3; Fanout = 57; REG Node = 'IR\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { clock IR[15] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.98 % ) " "Info: Total cell delay = 1.370 ns ( 44.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 55.02 % ) " "Info: Total interconnect delay = 1.676 ns ( 55.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock IR[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 IR[15] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.726 ns + Longest register pin " "Info: + Longest register to pin delay is 9.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IR\[15\] 1 REG LC_X12_Y14_N3 57 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y14_N3; Fanout = 57; REG Node = 'IR\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { IR[15] } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.132 ns) + CELL(0.280 ns) 2.412 ns Mux116~678 2 COMB LC_X14_Y20_N4 2 " "Info: 2: + IC(2.132 ns) + CELL(0.280 ns) = 2.412 ns; Loc. = LC_X14_Y20_N4; Fanout = 2; COMB Node = 'Mux116~678'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.412 ns" { IR[15] Mux116~678 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.312 ns) + CELL(0.280 ns) 4.004 ns Write_Read~100 3 COMB LC_X9_Y18_N9 2 " "Info: 3: + IC(1.312 ns) + CELL(0.280 ns) = 4.004 ns; Loc. = LC_X9_Y18_N9; Fanout = 2; COMB Node = 'Write_Read~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.592 ns" { Mux116~678 Write_Read~100 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.384 ns) + CELL(0.366 ns) 5.754 ns Write_Read~1 4 COMB LC_X17_Y20_N2 1 " "Info: 4: + IC(1.384 ns) + CELL(0.366 ns) = 5.754 ns; Loc. = LC_X17_Y20_N2; Fanout = 1; COMB Node = 'Write_Read~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.750 ns" { Write_Read~100 Write_Read~1 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(2.404 ns) 9.726 ns Write_Read 5 PIN PIN_J15 0 " "Info: 5: + IC(1.568 ns) + CELL(2.404 ns) = 9.726 ns; Loc. = PIN_J15; Fanout = 0; PIN Node = 'Write_Read'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.972 ns" { Write_Read~1 Write_Read } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.330 ns ( 34.24 % ) " "Info: Total cell delay = 3.330 ns ( 34.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.396 ns ( 65.76 % ) " "Info: Total interconnect delay = 6.396 ns ( 65.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.726 ns" { IR[15] Mux116~678 Write_Read~100 Write_Read~1 Write_Read } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.726 ns" { IR[15] Mux116~678 Write_Read~100 Write_Read~1 Write_Read } { 0.000ns 2.132ns 1.312ns 1.384ns 1.568ns } { 0.000ns 0.280ns 0.280ns 0.366ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.046 ns" { clock IR[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.046 ns" { clock clock~out0 IR[15] } { 0.000ns 0.000ns 1.676ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.726 ns" { IR[15] Mux116~678 Write_Read~100 Write_Read~1 Write_Read } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.726 ns" { IR[15] Mux116~678 Write_Read~100 Write_Read~1 Write_Read } { 0.000ns 2.132ns 1.312ns 1.384ns 1.568ns } { 0.000ns 0.280ns 0.280ns 0.366ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset Write_Read 6.752 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"Write_Read\" is 6.752 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns reset 1 PIN PIN_M21 93 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 93; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.980 ns) + CELL(0.075 ns) 2.780 ns Write_Read~1 2 COMB LC_X17_Y20_N2 1 " "Info: 2: + IC(1.980 ns) + CELL(0.075 ns) = 2.780 ns; Loc. = LC_X17_Y20_N2; Fanout = 1; COMB Node = 'Write_Read~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.055 ns" { reset Write_Read~1 } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(2.404 ns) 6.752 ns Write_Read 3 PIN PIN_J15 0 " "Info: 3: + IC(1.568 ns) + CELL(2.404 ns) = 6.752 ns; Loc. = PIN_J15; Fanout = 0; PIN Node = 'Write_Read'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.972 ns" { Write_Read~1 Write_Read } "NODE_NAME" } } { "cpu.vhd" "" { Text "C:/altera/VHDL/chap4/cpu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.204 ns ( 47.45 % ) " "Info: Total cell delay = 3.204 ns ( 47.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.548 ns ( 52.55 % ) " "Info: Total interconnect delay = 3.548 ns ( 52.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.752 ns" { reset Write_Read~1 Write_Read } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.752 ns" { reset reset~out0 Write_Read~1 Write_Read } { 0.000ns 0.000ns 1.980ns 1.568ns } { 0.000ns 0.725ns 0.075ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}