reset_db1200.s

The preferred technique places the new YAMON in the opposite Flash bank (the Db1200 boards have two

1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1200_SYS_ADDR
	lw		t1, sys_wakesrc(t0)

	/* Clear sys_wakemsk to prevent false events */
	sw		zero, sys_wakemsk(t0)
	sync

	/* Clear sys_wakesrc */
	//sw		zero, sys_wakesrc(t0)
	sync

	/* Check for Hibernate Reset first */
	andi	t2, t1, 0x04
	bne		zero, t2, hibernatereset
	nop

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne		zero, t2, hardwarereset
	nop

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne		zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	beq		zero, zero, runtimereset
	nop

/************************************************************************/

hardwarereset:
runtimereset:
hibernatereset:
	/*
	 * Step 1) Initialize DRAM
	 * Step 2) Initialize board
	 * Step 3) Invoke application
	 */
	bal 	initDRAM
	nop 
   	bal		initBOARD
	nop
	beq		zero, zero, alldone
	nop	 

sleepwakeup:
	/*
	 * Step 1) Wakeup DRAM
	 * Step 2) Initialize board
	 * Step 3) Resume application
	 */
  	bal		wakeupDRAM	
  	nop
	bal		initBOARD
	nop
	la		t0, AU1200_SYS_ADDR
	lw		sp, sys_scratch0(t0)
	lw		ra, sys_scratch1(t0)
	jr		ra
	nop

/*************************************************************************/

initDRAM:

	/* Only perform DRAM init if running from ROM/Flash */
	addu	t2, ra, zero	/* preserve ra */
    b		getPC
    nop

getPC:
    lui		t0, 0x1F00      /* ROM/flash address? */
    and		t1, t0, ra
	addu	ra, t2, zero	/* restore ra */
    bne		t0, t1, initDDRdone
    nop

	/* wait 1mS before setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

initDDR2:
#ifndef USE_S6	   
	li		t1, MEM_SDCONFIGA_DDR2
	li		t2, MEM_SDCONFIGB_DDR2
	li		t3, MEM_SDMODE0_DDR2
	li		t4, MEM_SDMODE1_DDR2
	li		v0, MEM_MR0_DDR2
	li		v1, MEM_MR1_DDR2
#else
	lw		t1, MEM_SDCONFIGA(a0)
	lw		t2, MEM_SDCONFIGB(a0)
	lw		t3, MEM_SDMODE(a0)
	lw		t4, MEM_SDMODE(a0)
	lw		v0, MEM_MR0(a0)
	lw		v1, MEM_MR1(a0)
#endif
	li		t5, MEM_SDADDR0_DDR2
	li		t6, MEM_SDADDR1_DDR2
	li		a2, MEM_MR2_DDR2
	li		a3, MEM_MR3_DDR2

	li		t0, AU1200_MEM_ADDR
	or		t2, MEM_SDCONFIGB_BB /* block LCD/MAE during init */
	sw		t1, mem_sdconfiga(t0)
	sync
	sw		t2, mem_sdconfigb(t0)
	sync
	sw		t3, mem_sdmode0(t0)
	sw		t4, mem_sdmode1(t0)
	sw		t5, mem_sdaddr0(t0)
	sw		t6, mem_sdaddr1(t0)
	sync

	/*
	 * Initialization per Micron data sheet, page 72:
	 * 0. Power sequence
	 * 1. 200us delay
	 * 2. NOP w/ CKE
	 * 3. PRECHARGE ALL
	 * 4. LOAD MODE REGISTER for the extended mode register (normal, not reduced, drive strength)
	 * 5. LOAD MODE REGISTER for the normal mode register (DLL reset activated)
	 * 6. 200 clocks of idle
	 * 7. PRECHARGE ALL
	 * 8. AUTO REFRESH x 2
	 * 9. LOAD MODE REGISTER (DLL reset de-activated)
	 * Devices are now ready for use.
	 */

	/* NOP w/ CKE */
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync

	/* PRECHARGE ALL */
	sw		zero, mem_sdprecmd(t0)
	sync

	/* LOAD MODE REGISTER extended mode register 3 */
	sw		a3, mem_sdwrmd0(t0)		
	sync
	sw		a3, mem_sdwrmd1(t0)		
	sync

	/* LOAD MODE REGISTER extended mode register 2 */
	sw		a2, mem_sdwrmd0(t0)		
	sync
	sw		a2, mem_sdwrmd1(t0)		
	sync

	/* LOAD MODE REGISTER extended mode register 1 */
	sw		v1, mem_sdwrmd0(t0)		
	sync
	sw		v1, mem_sdwrmd1(t0)		
	sync

	/* LOAD MODE REGISTER normal mode register DLL reset */
#define MR0_DLL 0x0100
	ori		t1, v0, MR0_DLL
	sw		t1, mem_sdwrmd0(t0)
	sync
	sw		t1, mem_sdwrmd1(t0)
	sync

	/* 200 clocks of idle */
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync

	/* PRECHARGE ALL */
	sw		zero, mem_sdprecmd(t0)
	sync

	/* AUTO REFRESH x 2 */
	sw		zero, mem_sdautoref(t0)
	sync
	sw		zero, mem_sdautoref(t0)
	sync

	/* LOAD MODE REGISTER normal mode register */
	sw		v0, mem_sdwrmd0(t0)
	sync
	sw		v0, mem_sdwrmd1(t0)
	sync

initDDRdone:
	/* Enable refresh */
	li		t0, AU1200_MEM_ADDR
	lw		t1, mem_sdconfiga(t0)
	li		t2, MEM_SDCONFIGA_E
	or		t1, t2, t1
	sw		t1, mem_sdconfiga(t0)
	sync

	/* Allow MAE/LCD */
	lw		t1, mem_sdconfigb(t0)
	li		t2, ~MEM_SDCONFIGB_BB
	and		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync

	/* wait 1mS after setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	jr		ra
	nop

/********************************************************************/

wakeupDRAM:	

#ifndef USE_S6
	li		t1, MEM_SDCONFIGA_DDR2
	li		t2, MEM_SDCONFIGB_DDR2
	li		t3, MEM_SDMODE0_DDR2
	li		t4, MEM_SDMODE1_DDR2
#else
	lw		t1, MEM_SDCONFIGA(a0)
	lw		t2, MEM_SDCONFIGB(a0)
	lw		t3, MEM_SDMODE(a0)
	lw		t4, MEM_SDMODE(a0)
#endif
	li		t5, MEM_SDADDR0_DDR2
	li		t6, MEM_SDADDR1_DDR2

	li		t0, AU1200_MEM_ADDR
	sw		t1, mem_sdconfiga(t0)
	sync
	sw		t2, mem_sdconfigb(t0)
	sync
	sw		t3, mem_sdmode0(t0)
	sw		t4, mem_sdmode1(t0)
	sw		t5, mem_sdaddr0(t0)
	sw		t6, mem_sdaddr1(t0)
	sync

	/* Assert DCKE - bring DDR out of self refresh */
	/* Note that two mem_sdsref are needed since state lost during sleep */
	sw		zero, mem_sdsref(t0)
	sw		zero, mem_sdsref(t0)

	/*
	 * Issue 80ns of NOPs
	 */ 
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
 	sw		t1, mem_sdconfigb(t0)
	sync 

	/*
	 * Perform burst refresh of 8K rows
	 */
	li		t1, 8192
burstrefresh:
	sw		zero, mem_sdautoref(t0)
	bne		zero, t1, burstrefresh
	addi	t1, t1, -1

	/* Enable refresh */
	lw		t1, mem_sdconfiga(t0)
	li		t2, MEM_SDCONFIGA_E
	or		t1, t2, t1
	sw		t1, mem_sdconfiga(t0)
	sync

 	jr	ra
	nop

/********************************************************************/

initBOARD:

	/*
	 * External and/or board-specific peripheral initialization
	 */

	/*
	 * Adjust 16-bit chip-selects if EB (RCE0 handled specially in yamon/init/reset/reset.S)
	 */
	mfc0 t0, CP0_Config
	andi t0, 0x8000
	beq zero, t0, 1f
	nop
	li		t2, 0x0200		/* mem_stcfg[BE]=1 */
	li		t0, AU1200_MEM_ADDR
	lw		t1, mem_stcfg1(t0)
	or		t1, t1, t2
	sw		t1, mem_stcfg1(t0)
	lw		t1, mem_stcfg2(t0)
	or		t1, t1, t2
	sw		t1, mem_stcfg2(t0)
	sync
1:

	/*
	 * Establish MUXed pin functionality
	 *
	 * 31:DMA=1  DMA_REQ1
	 * 30:S0A=1  SD0
	 * 29:S1A=0  PCMCIA
	 * 28:LP0=1  LCD_PWM0
	 * 27:LP1=1  LCD_PWM1
	 * 26:LD=1   LCD_D16
	 * 25:LD8=1  LCD_D8
	 * 24:LD1=1  LCD_D1
	 * 23:LD0=1  LCD_D0
	 * 21:P1A=00 PSC1
	 * 20:P1B=0  PSC1
	 * 19:FS3=1  FREQ3
	 * 17:P0A=01 PSC0
	 * 16:CS=0   EXTCLK0
	 * 15:CIM=1  CIM
	 * 14:P1C=1  PSC1
	 * 13:Reserved=1
	 * 12:U1T=0  UART1
	 * 11:U1R=1  UART1
	 * 10:EX1=0  GPIO3
	 *  9:EX0=1  EXTCLK0
	 *  8:U0R=1  UART0
	 *  7:MC=1   UART1
	 *  6:S0B=1  SD0
	 *  5:S0C=0  SD0
	 *  4:P0B=0  PSC0
	 *  3:U0T=0  U0TXD
	 *  2:S1B=1  PCMCIA
	 *  1:Reserved=0
	 *  0:Reserved=0
	 */
	li		t0, AU1200_SYS_ADDR
	li		t1, 0xDF8AEBC4
	sw		t1, sys_pinfunc(t0)

	/*
	 * Establish GPIO direction
	 *
	 * GPIO0 CIM_D0
	 * GPIO1 CIM_D1
	 * GPIO2 EXTCLK0 - I2S_MCLK
	 * GPIO3 Output LCD_CLK_IN_LED#
	 * GPIO4 Input DC DMA_REQ
	 * GPIO5 Input GPIO5_Switch
	 * GPIO6 SD_Card0_DAT2
	 * GPIO7 Input Board_IRQ#
	 * GPIO8 SD_CARD0_DAT1
	 * GPIO9  U1_CTS
	 * GPIO10 U1_DSR
	 * GPIO11 PSC1_D0
	 * GPIO12 DMA_REQ1 for IDE
	 * GPIO13 U1_RTS
	 * GPIO14 U1_DTR
	 * GPIO15 U1_TXD
	 * GPIO16 PSC0_SYNC1
	 * GPIO17 SD_Card0_CLK
	 * GPIO18 PSC0_D0
	 * GPIO19 SD_Card0_DAT0
	 * GPIO20 PSC1_SYNC0
	 * GPIO21 PSC1_SYNC1
	 * GPIO22 PSC1_D1
	 * GPIO23 I2S_MCLK_IN 
	 * GPIO24 PSC1_CLK
	 * GPIO25 PSC0_CLK
	 * GPIO26 SD_Card0_DAT3
	 * GPIO27 U0_TXD
	 * GPIO28 SD_Card0_CMD
	 * GPIO29 U0_RXD
	 * GPIO30 U1_RXD
	 * GPIO31 PSC0_D1
	 */
	li		t1, 0x000000B0
	sw		t1, sys_trioutclr(t0)		/* inputs enabled */
	li		t1, 0x00000008				/* turn on green led D3 */
	sw		t1, sys_outputclr(t0)
	sync

	/*
	 * Establish GPIO2 direction
	 *
	 * GPIO200 LCD_D0
	 * GPIO201 LCD_D1
	 * GPIO202 CIM_D2
	 * GPIO203 CIM_D3
	 * GPIO204 CIM_D4
	 * GPIO205 CIM_D5
	 * GPIO206 CIM_D6
	 * GPIO207 CIM_D7
	 * GPIO208 CIM_D8
	 * GPIO209 CIM_D9
	 * GPIO210 LCD_D8
	 * GPIO211 LCD_D16
	 * GPIO212 CIM_LS
	 * GPIO213 CIM_FS
	 * GPIO214 CIM_CLK
	 * GPIO215 Output NAND_FORCE_CE# and OTG_VBUS_ON#
	 */
	li		t0, AU1200_GPIO2_ADDR
	li		t1,3
	sw		t1,gpio2_enable(t0)
	sync
	li		t1,1
	sw		t1,gpio2_enable(t0)
	sync
	sw		zero,gpio2_inten(t0)
	sync
	li		t1,(1<<15)
	sw		t1,gpio2_dir(t0)
	sync
	li		t1,(1<<31)|(1<<15)		/* do not assert GPIO215 */
	sw		t1,gpio2_output(t0)
	sync

	/*
	 * Establish CLOCKing
	 *
	 * FREQ5: unused
	 * FREQ4: unused
	 * FREQ3: unused
	 * FREQ2: unused
	 * FREQ1: unused - 24MHz for PSC0 (SMBus and SPI)
	 * FREQ0: unused
	 */
	li		t0, AU1200_SYS_ADDR
	li		t1, (1<<12)|(1<<11)|(1<<10)
	sw		t1, sys_freqctrl0(t0)
	li		t1, (3<<22)|(1<<21)|(1<<20)
	sw		t1, sys_clksrc(t0)
	sync

	/* Take IDE/LAN/DC/CIM out of reset */
	li		t0, DB1200_BCSR_ADDR
	lh		t1, bcsr_resets(t0)
	ori		t1, 0x000F
	sh		t1, bcsr_resets(t0)
	sync

	/* Ensure PCMCIA interface disabled */
	li		t0, DB1200_BCSR_ADDR
	sh		zero, bcsr_pcmcia(t0)
	sync

	/* Ensure SD, CIM, LCD powered-off */
	li		t0, DB1200_BCSR_ADDR
	li		t1, 0x0020
	sh		t1, bcsr_board(t0)
	sync

	/* Ensure Board Interrupt Controller is disabled */
	li		t0, DB1200_BCSR_ADDR
	li		t1, 0xFFFF
	sh		t1, bcsr_icer(t0)
	sh		t1, bcsr_icmr(t0)
	sync

	jr		ra
	nop

/********************************************************************/

alldone:

	/*
	 * Prepare to invoke application main()
	 */
	 .set reorder

/********************************************************************/