defeqns.htm
来自「RS232-光纤的CPLD调制解调源程序」· HTM 代码 · 共 134 行
HTM
134 行
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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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CAN_TX <= (cTX_Tem AND SD);
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FDCPE_FDDI_TX: FDCPE port map (FDDI_TX,FDDI_TX_D,NOT fTX_Start,'0','0');
<br/> FDDI_TX_D <= ((NOT fTX_Over AND NOT CAN_RX)
<br/> OR (fTX_Over AND fTX_N AND NOT fTX_T)
<br/> OR (fTX_Over AND NOT fTX_N AND fTX_T));
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FDCPE_LED_RX: FDCPE port map (LED_RX,LED_RX_D,NOT fTX_Start,'0','0');
<br/> LED_RX_D <= ((fTX_Over AND NOT LED_RX.PIN)
<br/> OR (NOT fTX_Over AND NOT CAN_RX));
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FTCPE_LED_TX: FTCPE port map (LED_TX,LED_TX_T,NOT CLK,'0','0');
<br/> LED_TX_T <= ((NOT cTX_DataN(0) AND cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(0) AND
<br/> cTX_Data(1) AND NOT cTX_Data(3) AND LED_TX.PIN)
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(0) AND
<br/> NOT cTX_Data(1) AND NOT cTX_Data(3) AND NOT LED_TX.PIN));
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FTCPE_cTX_Data0: FTCPE port map (cTX_Data(0),cTX_Data_T(0),NOT CLK,'0','0');
<br/> cTX_Data_T(0) <= ((cTX_Data(1).EXP)
<br/> OR (NOT cTX_DataN(0) AND NOT cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(0))
<br/> OR (NOT cTX_DataN(0) AND NOT cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(0))
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(0) AND
<br/> cTX_Data(1))
<br/> OR (NOT cTX_DataN(0) AND fBit_Value AND NOT FDDI_RX AND
<br/> fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(0) AND cTX_Data(1) AND
<br/> cTX_Data(3))
<br/> OR (NOT cTX_DataN(0) AND NOT fBit_Value AND FDDI_RX AND
<br/> fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(0) AND NOT cTX_Data(1) AND
<br/> cTX_Data(3)));
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FTCPE_cTX_Data1: FTCPE port map (cTX_Data(1),cTX_Data_T(1),NOT CLK,'0','0');
<br/> cTX_Data_T(1) <= ((cTX_DataN(0) AND NOT cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(1))
<br/> OR (cTX_DataN(0) AND NOT cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(1))
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(1))
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(1)));
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FTCPE_cTX_Data3: FTCPE port map (cTX_Data(3),cTX_Data_T(3),NOT CLK,'0','0');
<br/> cTX_Data_T(3) <= ((NOT cTX_DataN(0) AND cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(3))
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(3)));
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FTCPE_cTX_DataN0: FTCPE port map (cTX_DataN(0),cTX_DataN_T(0),NOT CLK,'0','0');
<br/> cTX_DataN_T(0) <= ((NOT cTX_DataN(1) AND fBit_Value AND NOT FDDI_RX AND
<br/> fBit_Bit(0) AND fBit_Bit(1))
<br/> OR (NOT cTX_DataN(1) AND NOT fBit_Value AND FDDI_RX AND
<br/> fBit_Bit(0) AND fBit_Bit(1)));
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FTCPE_cTX_DataN1: FTCPE port map (cTX_DataN(1),cTX_DataN_T(1),NOT CLK,'0','0');
<br/> cTX_DataN_T(1) <= ((cTX_DataN(0) AND NOT cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1))
<br/> OR (cTX_DataN(0) AND NOT cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1))
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(0) AND
<br/> cTX_Data(1) AND NOT cTX_Data(3))
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(0) AND
<br/> NOT cTX_Data(1) AND NOT cTX_Data(3)));
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FTCPE_cTX_Tem: FTCPE port map (cTX_Tem,cTX_Tem_T,NOT CLK,'0','0');
<br/> cTX_Tem_T <= ((NOT cTX_DataN(0) AND cTX_DataN(1) AND fBit_Value AND
<br/> NOT FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND NOT cTX_Data(0) AND
<br/> cTX_Data(1) AND NOT cTX_Data(3) AND NOT cTX_Tem)
<br/> OR (NOT cTX_DataN(0) AND cTX_DataN(1) AND NOT fBit_Value AND
<br/> FDDI_RX AND fBit_Bit(0) AND fBit_Bit(1) AND cTX_Data(0) AND
<br/> NOT cTX_Data(1) AND NOT cTX_Data(3) AND cTX_Tem));
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FDCPE_fBit_Bit0: FDCPE port map (fBit_Bit(0),fBit_Bit_D(0),NOT CLK,'0','0');
<br/> fBit_Bit_D(0) <= ((fBit_Value AND NOT FDDI_RX AND fBit_Bit(0))
<br/> OR (NOT fBit_Value AND FDDI_RX AND fBit_Bit(0)));
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FDCPE_fBit_Bit1: FDCPE port map (fBit_Bit(1),fBit_Bit_D(1),NOT CLK,'0','0');
<br/> fBit_Bit_D(1) <= ((NOT fBit_Bit(0) AND NOT fBit_Bit(1))
<br/> OR (fBit_Value AND NOT FDDI_RX AND fBit_Bit(0) AND
<br/> fBit_Bit(1))
<br/> OR (NOT fBit_Value AND FDDI_RX AND fBit_Bit(0) AND
<br/> fBit_Bit(1)));
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FDCPE_fBit_Value: FDCPE port map (fBit_Value,NOT FDDI_RX,NOT CLK,'0','0');
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FDCPE_fTX_CLK0: FDCPE port map (fTX_CLK(0),fTX_CLK_D(0),NOT CLK,'0','0');
<br/> fTX_CLK_D(0) <= (NOT fTX_CLK(0) AND NOT fTX_CLK(1) AND NOT fTX_CLK(2) AND
<br/> NOT fTX_CLK(3));
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FDCPE_fTX_CLK1: FDCPE port map (fTX_CLK(1),'0',NOT CLK,'0','0');
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FDCPE_fTX_CLK2: FDCPE port map (fTX_CLK(2),'0',NOT CLK,'0','0');
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FDCPE_fTX_CLK3: FDCPE port map (fTX_CLK(3),'0',NOT CLK,'0','0');
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FDCPE_fTX_N: FDCPE port map (fTX_N,fTX_Over,NOT fTX_Start,'0','0');
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FDCPE_fTX_Over: FDCPE port map (fTX_Over,fTX_Over_D,NOT fTX_Start,'0','0');
<br/> fTX_Over_D <= (fTX_Over AND fTX_N);
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FTCPE_fTX_Start: FTCPE port map (fTX_Start,fTX_Start_T,NOT CLK,'0','0');
<br/> fTX_Start_T <= (NOT fTX_CLK(0) AND NOT fTX_CLK(1) AND NOT fTX_CLK(2) AND
<br/> NOT fTX_CLK(3));
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FDCPE_fTX_T: FDCPE port map (fTX_T,fTX_T_D,NOT fTX_Start,'0','0');
<br/> fTX_T_D <= ((fTX_Over AND fTX_T)
<br/> OR (NOT fTX_Over AND NOT CAN_RX));
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Register Legend:
<br/> FDCPE (Q,D,C,CLR,PRE);
<br/> FTCPE (Q,D,C,CLR,PRE);
<br/> LDCP (Q,D,G,CLR,PRE);
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