📄 cantofddi.rpt
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cpldfit: version J.30 Xilinx Inc.
Fitter Report
Design Name: CANtoFDDI Date: 10-30-2007, 3:25PM
Device Used: XC9536-10-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
21 /36 ( 58%) 45 /180 ( 25%) 28 /72 ( 39%) 20 /36 ( 56%) 8 /34 ( 24%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 16/18 21/36 21 40/90 2/17
FB2 5/18 7/36 7 5/90 2/17
----- ----- ----- -----
21/36 28/72 45/180 4/34
* - Resource is exhausted
** Global Control Resources **
The complement of 'CLK' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 3 3 | I/O : 7 28
Output : 2 2 | GCK/IO : 1 3
Bidirectional : 2 2 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 8 8
** Power Data **
There are 21 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 4 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
LED_TX 2 10 FB1_14 13 I/O I/O STD FAST SET
LED_RX 3 4 FB1_15 14 I/O I/O STD FAST SET
CAN_TX 1 2 FB2_4 37 I/O O STD FAST
FDDI_TX 4 5 FB2_16 20 I/O O STD FAST RESET
** 17 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
fTX_Start 1 4 FB1_3 STD SET
fTX_CLK<0> 1 4 FB1_4 STD RESET
fBit_Value 1 1 FB1_5 STD RESET
fTX_Over 2 3 FB1_6 STD RESET
fTX_N 2 2 FB1_7 STD RESET
fBit_Bit<0> 2 3 FB1_8 STD RESET
cTX_Tem 2 10 FB1_9 STD RESET
cTX_DataN<0> 2 5 FB1_10 STD RESET
cTX_Data<3> 2 7 FB1_11 STD RESET
fTX_T 3 4 FB1_12 STD RESET
fBit_Bit<1> 3 4 FB1_13 STD RESET
cTX_DataN<1> 4 9 FB1_16 STD RESET
cTX_Data<1> 4 7 FB1_17 STD RESET
cTX_Data<0> 6 9 FB1_18 STD RESET
fTX_CLK<3> 0 0 FB2_15 STD RESET
fTX_CLK<2> 0 0 FB2_17 STD RESET
fTX_CLK<1> 0 0 FB2_18 STD RESET
** 4 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CLK FB1_7 1 GCK/I/O GCK
CAN_RX FB2_2 38 I/O I
FDDI_RX FB2_14 22 I/O I
SD FB2_15 21 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 40 I/O
(unused) 0 0 0 5 FB1_2 41 I/O
fTX_Start 1 0 0 4 FB1_3 43 GCK/I/O (b)
fTX_CLK<0> 1 0 0 4 FB1_4 42 I/O (b)
fBit_Value 1 0 0 4 FB1_5 44 GCK/I/O (b)
fTX_Over 2 0 0 3 FB1_6 2 I/O (b)
fTX_N 2 0 0 3 FB1_7 1 GCK/I/O GCK
fBit_Bit<0> 2 0 0 3 FB1_8 3 I/O (b)
cTX_Tem 2 0 0 3 FB1_9 5 I/O (b)
cTX_DataN<0> 2 0 0 3 FB1_10 6 I/O (b)
cTX_Data<3> 2 0 0 3 FB1_11 7 I/O (b)
fTX_T 3 0 0 2 FB1_12 8 I/O (b)
fBit_Bit<1> 3 0 0 2 FB1_13 12 I/O (b)
LED_TX 2 0 0 3 FB1_14 13 I/O I/O
LED_RX 3 0 0 2 FB1_15 14 I/O I/O
cTX_DataN<1> 4 0 0 1 FB1_16 16 I/O (b)
cTX_Data<1> 4 0 \/1 0 FB1_17 18 I/O (b)
cTX_Data<0> 6 1<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: CAN_RX 8: cTX_DataN<0> 15: fTX_CLK<1>
2: FDDI_RX 9: cTX_DataN<1> 16: fTX_CLK<2>
3: LED_RX.PIN 10: cTX_Tem 17: fTX_CLK<3>
4: LED_TX.PIN 11: fBit_Bit<0> 18: fTX_N
5: cTX_Data<0> 12: fBit_Bit<1> 19: fTX_Over
6: cTX_Data<1> 13: fBit_Value 20: fTX_Start
7: cTX_Data<3> 14: fTX_CLK<0> 21: fTX_T
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
fTX_Start .............XXXX....................... 4 4
fTX_CLK<0> .............XXXX....................... 4 4
fBit_Value .X...................................... 1 1
fTX_Over .................XXX.................... 3 3
fTX_N ..................XX.................... 2 2
fBit_Bit<0> .X........X.X........................... 3 3
cTX_Tem .X..XXXXXXXXX........................... 10 10
cTX_DataN<0> .X......X.XXX........................... 5 5
cTX_Data<3> .X....XXX.XXX........................... 7 7
fTX_T X.................XXX................... 4 4
fBit_Bit<1> .X........XXX........................... 4 4
LED_TX .X.XXXXXX.XXX........................... 10 10
LED_RX X.X...............XX.................... 4 4
cTX_DataN<1> .X..XXXXX.XXX........................... 9 9
cTX_Data<1> .X...X.XX.XXX........................... 7 7
cTX_Data<0> .X..XXXXX.XXX........................... 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 7/29
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 39 I/O
(unused) 0 0 0 5 FB2_2 38 I/O I
(unused) 0 0 0 5 FB2_3 36 GTS/I/O
CAN_TX 1 0 0 4 FB2_4 37 I/O O
(unused) 0 0 0 5 FB2_5 34 GTS/I/O
(unused) 0 0 0 5 FB2_6 33 GSR/I/O
(unused) 0 0 0 5 FB2_7 32 I/O
(unused) 0 0 0 5 FB2_8 31 I/O
(unused) 0 0 0 5 FB2_9 30 I/O
(unused) 0 0 0 5 FB2_10 29 I/O
(unused) 0 0 0 5 FB2_11 28 I/O
(unused) 0 0 0 5 FB2_12 27 I/O
(unused) 0 0 0 5 FB2_13 23 I/O
(unused) 0 0 0 5 FB2_14 22 I/O I
fTX_CLK<3> 0 0 0 5 FB2_15 21 I/O I
FDDI_TX 4 0 0 1 FB2_16 20 I/O O
fTX_CLK<2> 0 0 0 5 FB2_17 19 I/O (b)
fTX_CLK<1> 0 0 0 5 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: CAN_RX 4: fTX_N 6: fTX_Start
2: SD 5: fTX_Over 7: fTX_T
3: cTX_Tem
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
CAN_TX .XX..................................... 2 2
fTX_CLK<3> ........................................ 0 0
FDDI_TX X..XXXX................................. 5 5
fTX_CLK<2> ........................................ 0 0
fTX_CLK<1> ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
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