📄 os_cpu_a.lst
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ON HANDLER
368 00000130 ;
369 00000130 ; Register Usage: R0 Exception Type
370 00000130 ; R1
371 00000130 ; R2
372 00000130 ; R3 Return PC
373 00000130 ;*******************************************************
*************************************************
374 00000130
375 00000130 AREA CODE, CODE, READONLY
376 00000130 CODE32
377 00000130
378 00000130 OS_CPU_ARM_ExceptDataAbortHndlr
379 00000130 E24EE008 SUB LR, LR, #8 ; LR offset to retu
rn from this except
ion: -8.
380 00000134 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
381 00000138 E1A0300E MOV R3, LR ; Save link registe
r.
382 0000013C E3A00004 MOV R0, #OS_CPU_ARM_EXCEPT_DATA_ABO
RT
; Set exception ID
to OS_CPU_ARM_EXCEP
T_DATA_ABORT.
383 00000140 EA00000E B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
384 00000144
385 00000144
386 00000144 ;*******************************************************
*************************************************
387 00000144 ; ADDRESS ABORT EXCEP
TION HANDLER
388 00000144 ;
389 00000144 ; Register Usage: R0 Exception Type
390 00000144 ; R1
391 00000144 ; R2
ARM Macro Assembler Page 11
392 00000144 ; R3 Return PC
393 00000144 ;*******************************************************
*************************************************
394 00000144
395 00000144 AREA CODE, CODE, READONLY
396 00000144 CODE32
397 00000144
398 00000144 OS_CPU_ARM_ExceptAddrAbortHndlr
399 00000144 E24EE008 SUB LR, LR, #8 ; LR offset to retu
rn from this except
ion: -8.
400 00000148 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
401 0000014C E1A0300E MOV R3, LR ; Save link registe
r.
402 00000150 E3A00005 MOV R0, #OS_CPU_ARM_EXCEPT_ADDR_ABO
RT
; Set exception ID
to OS_CPU_ARM_EXCEP
T_ADDR_ABORT.
403 00000154 EA000009 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
404 00000158
405 00000158
406 00000158 ;*******************************************************
*************************************************
407 00000158 ; INTERRUPT REQUEST EXC
EPTION HANDLER
408 00000158 ;
409 00000158 ; Register Usage: R0 Exception Type
410 00000158 ; R1
411 00000158 ; R2
412 00000158 ; R3 Return PC
413 00000158 ;*******************************************************
*************************************************
414 00000158
415 00000158 AREA CODE, CODE, READONLY
416 00000158 CODE32
417 00000158
418 00000158 OS_CPU_ARM_ExceptIrqHndlr
419 00000158 E24EE004 SUB LR, LR, #4 ; LR offset to retu
rn from this except
ion: -4.
420 0000015C E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
421 00000160 E1A0300E MOV R3, LR ; Save link registe
r.
422 00000164 E3A00006 MOV R0, #OS_CPU_ARM_EXCEPT_IRQ ; Se
t exception ID to O
S_CPU_ARM_EXCEPT_IR
Q.
423 00000168 EA000004 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
424 0000016C
425 0000016C
426 0000016C ;*******************************************************
*************************************************
ARM Macro Assembler Page 12
427 0000016C ; FAST INTERRUPT REQUEST E
XCEPTION HANDLER
428 0000016C ;
429 0000016C ; Register Usage: R0 Exception Type
430 0000016C ; R1
431 0000016C ; R2
432 0000016C ; R3 Return PC
433 0000016C ;*******************************************************
*************************************************
434 0000016C
435 0000016C AREA CODE, CODE, READONLY
436 0000016C CODE32
437 0000016C
438 0000016C OS_CPU_ARM_ExceptFiqHndlr
439 0000016C E24EE004 SUB LR, LR, #4 ; LR offset to retu
rn from this except
ion: -4.
440 00000170 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
441 00000174 E1A0300E MOV R3, LR ; Save link registe
r.
442 00000178 E3A00007 MOV R0, #OS_CPU_ARM_EXCEPT_FIQ ; Se
t exception ID to O
S_CPU_ARM_EXCEPT_FI
Q.
443 0000017C EAFFFFFF B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
444 00000180
445 00000180
446 00000180 ;*******************************************************
*************************************************
447 00000180 ; GLOBAL EXCEPTION
HANDLER
448 00000180 ;
449 00000180 ; Register Usage: R0 Exception Type
450 00000180 ; R1 Exception's SPSR
451 00000180 ; R2 Old CPU mode
452 00000180 ; R3 Return PC
453 00000180 ;*******************************************************
*************************************************
454 00000180
455 00000180 AREA CODE, CODE, READONLY
456 00000180 CODE32
457 00000180
458 00000180 OS_CPU_ARM_ExceptHndlr
459 00000180 E14F1000 MRS R1, SPSR ; Save CPSR (i.e. e
xception's SPSR).
460 00000184
461 00000184 ; DETERMINE IF WE INTERRUPTED A TASK OR ANOTHER LOWER PR
IORITY EXCEPTION:
462 00000184 ; SPSR.Mode = SVC : task,
463 00000184 ; SPSR.Mode = FIQ, IRQ, ABT, UND : other exceptions,
464 00000184 ; SPSR.Mode = USR : *unsupported state*
.
465 00000184 E201201F AND R2, R1, #OS_CPU_ARM_MODE_MASK
466 00000188 E3520013 CMP R2, #OS_CPU_ARM_MODE_SVC
467 0000018C 1A00001F BNE OS_CPU_ARM_ExceptHndlr_BreakExc
ept
ARM Macro Assembler Page 13
468 00000190
469 00000190
470 00000190 ;*******************************************************
*************************************************
471 00000190 ; EXCEPTION HANDLER: TA
SK INTERRUPTED
472 00000190 ;
473 00000190 ; Register Usage: R0 Exception Type
474 00000190 ; R1 Exception's SPSR
475 00000190 ; R2 Exception's CPSR
476 00000190 ; R3 Return PC
477 00000190 ; R4 Exception's SP
478 00000190 ;*******************************************************
*************************************************
479 00000190
480 00000190 AREA CODE, CODE, READONLY
481 00000190 CODE32
482 00000190
483 00000190 OS_CPU_ARM_ExceptHndlr_BreakTask
484 00000190 E10F2000 MRS R2, CPSR ; Save exception's
CPSR.
485 00000194 E1A0400D MOV R4, SP ; Save exception's
stack pointer.
486 00000198
487 00000198 ; Change to SVC mode & disable interruptions.
488 00000198 E321F0D3 MSR CPSR_c, #(OS_CPU_ARM_CONTROL_IN
T_DIS | OS_CPU_ARM_MODE_SVC)
489 0000019C
490 0000019C ; SAVE TASK'S CONTEXT ONTO TASK'S STACK:
491 0000019C E92D0008 STMFD SP!, {R3} ; Push task's PC,
492 000001A0 E92D4000 STMFD SP!, {LR} ; Push task's LR,
493 000001A4 E92D1FE0 STMFD SP!, {R5-R12} ; Push task's R
12-R5,
494 000001A8 E8B403E0 LDMFD R4!, {R5-R9} ; Move task's R4
-R0 from exception
stack to task's sta
ck.
495 000001AC E92D03E0 STMFD SP!, {R5-R9}
496 000001B0 E92D0002 STMFD SP!, {R1} ; Push task's CPS
R (i.e. exception S
PSR).
497 000001B4
498 000001B4 ; if (OSRunning == 1)
499 000001B4 E59F1098 LDR R1, __OS_Running
500 000001B8 E5D11000 LDRB R1, [R1]
501 000001BC E3510001 CMP R1, #1
502 000001C0 1A000006 BNE OS_CPU_ARM_ExceptHndlr_BreakTas
k_1
503 000001C4
504 000001C4 ; HANDLE NESTING COUNTER:
505 000001C4 E59F309C LDR R3, __OS_IntNesting
; OSIntNesting++;
506 000001C8 E5D34000 LDRB R4, [R3]
507 000001CC E2844001 ADD R4, R4, #1
508 000001D0 E5C34000 STRB R4, [R3]
509 000001D4
ARM Macro Assembler Page 14
510 000001D4 E59F3084 LDR R3, __OS_TCBCur ; OSTCBCur->O
STCBStkPtr = SP;
511 000001D8 E5934000 LDR R4, [R3]
512 000001DC E584D000 STR SP, [R4]
513 000001E0
514 000001E0 OS_CPU_ARM_ExceptHndlr_BreakTask_1
515 000001E0 E12FF002 MSR CPSR_cxsf, R2 ; RESTORE INTERRU
PTED MODE.
516 000001E4
517 000001E4 ; EXECUTE EXCEPTION HANDLER:
518 000001E4 E59F1088 LDR R1, __OS_CPU_ExceptHndlr ; OS_C
PU_ExceptHndlr(exce
pt_type = R0);
519 000001E8 E1A0E00F MOV LR, PC
520 000001EC E12FFF11 BX R1
521 000001F0
522 000001F0 ; Adjust exception stack pointer. This is needed becaus
e
523 000001F0 ; exception stack is not used when restoring task contex
t.
524 000001F0 E28DD038 ADD SP, SP, #(14 * 4)
525 000001F4
526 000001F4 ; Change to SVC mode & disable interruptions.
527 000001F4 E321F0D3 MSR CPSR_c, #(OS_CPU_ARM_CONTROL_IN
T_DIS | OS_CPU_ARM_MODE_SVC)
528 000001F8
529 000001F8 ; Call OSIntExit(). This call MAY never return if a rea
dy
530 000001F8 ; task with higher priority than the interrupted one is
531 000001F8 ; found.
532 000001F8 E59F0070 LDR R0, __OS_IntExit
533 000001FC E1A0E00F MOV LR, PC
534 00000200 E12FFF10 BX R0
535 00000204
536 00000204 ; RESTORE NEW TASK'S CONTEXT:
537 00000204 E8BD0001 LDMFD SP!, {R0} ; Pop new task's
CPSR,
538 00000208 E16FF000 MSR SPSR_cxsf, R0
539 0000020C
540 0000020C E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^ ; Pop
new task's context
.
541 00000210
542 00000210
543 00000210 ;*******************************************************
*************************************************
544 00000210 ; EXCEPTION HANDLER: EXCEP
TION INTERRUPTED
545 00000210 ;
546 00000210 ; Register Usage: R0 Exception Type
547 00000210 ; R1
548 00000210 ; R2
549 00000210 ; R3
550 00000210 ;*******************************************************
*************************************************
551 00000210
552 00000210 OS_CPU_ARM_ExceptHndlr_BreakExcept
553 00000210 E10F2000 MRS R2, CPSR ; Save exception's
ARM Macro Assembler Page 15
CPSR.
554 00000214
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