📄 os_cpu_a.lst
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178 0000004C
179 0000004C
180 0000004C ;*******************************************************
**************************************************
181 0000004C ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
182 0000004C ;
183 0000004C ; Note(s) : 1) OSCtxSw() is called in SVC mode with BOTH
FIQ and IRQ interrupts DISABLED.
184 0000004C ;
185 0000004C ; 2) The pseudo-code for OSCtxSw() is:
186 0000004C ; a) Save the current task's context onto t
he current task's stack,
187 0000004C ; b) OSTCBCur->OSTCBStkPtr = SP;
188 0000004C ; c) OSTaskSwHook();
189 0000004C ; d) OSPrioCur = OSPrioHighRdy;
190 0000004C ; e) OSTCBCur = OSTCBHighRdy;
191 0000004C ; f) SP = OSTCBHighRdy->
ARM Macro Assembler Page 6
OSTCBStkPtr;
192 0000004C ; g) Restore the new task's context from th
e new task's stack,
193 0000004C ; h) Return to new task's code.
194 0000004C ;
195 0000004C ; 3) Upon entry:
196 0000004C ; OSTCBCur points to the OS_TCB of the
task to suspend,
197 0000004C ; OSTCBHighRdy points to the OS_TCB of the
task to resume.
198 0000004C ;*******************************************************
**************************************************
199 0000004C
200 0000004C AREA CODE, CODE, READONLY
201 0000004C CODE32
202 0000004C
203 0000004C OSCtxSw
204 0000004C ; SAVE CURRENT TASK'S CONTEXT:
205 0000004C E92D4000 STMFD SP!, {LR} ; Push return a
ddress,
206 00000050 E92D4000 STMFD SP!, {LR}
207 00000054 E92D1FFF STMFD SP!, {R0-R12} ; Push regist
ers,
208 00000058 E10F0000 MRS R0, CPSR ; Push current
CPSR,
209 0000005C E31E0001 TST LR, #1 ; See if called
from Thumb mode,
210 00000060 13800020 ORRNE R0, R0, #OS_CPU_ARM_CONTROL_THU
MB
; If yes, set t
he T-bit.
211 00000064 E92D0001 STMFD SP!, {R0}
212 00000068
213 00000068 E59F01F0 LDR R0, __OS_TCBCur ; OSTCBCur->OST
CBStkPtr = SP;
214 0000006C E5901000 LDR R1, [R0]
215 00000070 E581D000 STR SP, [R1]
216 00000074
217 00000074 E59F01F0 LDR R0, __OS_TaskSwHook
; OSTaskSwHook();
218 00000078 E1A0E00F MOV LR, PC
219 0000007C E12FFF10 BX R0
220 00000080
221 00000080 E59F01D0 LDR R0, __OS_PrioCur ; OSPrioCur =
OSPrioHighRdy;
222 00000084 E59F11D0 LDR R1, __OS_PrioHighRdy
223 00000088 E5D12000 LDRB R2, [R1]
224 0000008C E5C02000 STRB R2, [R0]
225 00000090
226 00000090 E59F01C8 LDR R0, __OS_TCBCur ; OSTCBCur = O
STCBHighRdy;
227 00000094 E59F11C8 LDR R1, __OS_TCBHighRdy
228 00000098 E5912000 LDR R2, [R1]
229 0000009C E5802000 STR R2, [R0]
230 000000A0
231 000000A0 E592D000 LDR SP, [R2] ; SP = OSTCBHighRdy
->OSTCBStkPtr;
232 000000A4
233 000000A4 ; RESTORE NEW TASK'S CONTEXT:
ARM Macro Assembler Page 7
234 000000A4 E8BD0001 LDMFD SP!, {R0} ; Pop new task's
CPSR,
235 000000A8 E16FF000 MSR SPSR_cxsf, R0
236 000000AC
237 000000AC E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^ ; Pop
new task's context
.
238 000000B0
239 000000B0
240 000000B0 ;*******************************************************
**************************************************
241 000000B0 ; PERFORM A CONTEXT SWITCH (From int
errupt level) - OSIntCtxSw()
242 000000B0 ;
243 000000B0 ; Note(s) : 1) OSIntCtxSw() is called in SVC mode with B
OTH FIQ and IRQ interrupts DISABLED.
244 000000B0 ;
245 000000B0 ; 2) The pseudo-code for OSCtxSw() is:
246 000000B0 ; a) OSTaskSwHook();
247 000000B0 ; b) OSPrioCur = OSPrioHighRdy;
248 000000B0 ; c) OSTCBCur = OSTCBHighRdy;
249 000000B0 ; d) SP = OSTCBHighRdy->
OSTCBStkPtr;
250 000000B0 ; e) Restore the new task's context from th
e new task's stack,
251 000000B0 ; f) Return to new task's code.
252 000000B0 ;
253 000000B0 ; 3) Upon entry:
254 000000B0 ; OSTCBCur points to the OS_TCB of the
task to suspend,
255 000000B0 ; OSTCBHighRdy points to the OS_TCB of the
task to resume.
256 000000B0 ;*******************************************************
**************************************************
257 000000B0
258 000000B0 AREA CODE, CODE, READONLY
259 000000B0 CODE32
260 000000B0
261 000000B0 OSIntCtxSw
262 000000B0 E59F01B4 LDR R0, __OS_TaskSwHook
; OSTaskSwHook();
263 000000B4 E1A0E00F MOV LR, PC
264 000000B8 E12FFF10 BX R0
265 000000BC
266 000000BC E59F0194 LDR R0, __OS_PrioCur ; OSPrioCur =
OSPrioHighRdy;
267 000000C0 E59F1194 LDR R1, __OS_PrioHighRdy
268 000000C4 E5D12000 LDRB R2, [R1]
269 000000C8 E5C02000 STRB R2, [R0]
270 000000CC
271 000000CC E59F018C LDR R0, __OS_TCBCur ; OSTCBCur = O
STCBHighRdy;
272 000000D0 E59F118C LDR R1, __OS_TCBHighRdy
273 000000D4 E5912000 LDR R2, [R1]
274 000000D8 E5802000 STR R2, [R0]
275 000000DC
276 000000DC E592D000 LDR SP, [R2] ; SP = OSTCBHighRdy
->OSTCBStkPtr;
ARM Macro Assembler Page 8
277 000000E0
278 000000E0 ; RESTORE NEW TASK'S CONTEXT:
279 000000E0 E8BD0001 LDMFD SP!, {R0} ; Pop new task's
CPSR,
280 000000E4 E16FF000 MSR SPSR_cxsf, R0
281 000000E8
282 000000E8 E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^ ; Pop
new task's context
.
283 000000EC
284 000000EC
285 000000EC ;*******************************************************
*************************************************
286 000000EC ; RESET EXCEPTION
HANDLER
287 000000EC ;
288 000000EC ; Register Usage: R0 Exception Type
289 000000EC ; R1
290 000000EC ; R2
291 000000EC ; R3 Return PC
292 000000EC ;*******************************************************
*************************************************
293 000000EC
294 000000EC AREA CODE, CODE, READONLY
295 000000EC CODE32
296 000000EC
297 000000EC OS_CPU_ARM_ExceptResetHndlr
298 000000EC ; LR offset to return from this exception: 0.
299 000000EC ; (there is no way to return from a RESET exception).
300 000000EC E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
301 000000F0 E1A0300E MOV R3, LR ; Save link registe
r.
302 000000F4 E3A00000 MOV R0, #OS_CPU_ARM_EXCEPT_RESET ;
Set exception ID to
OS_CPU_ARM_EXCEPT_
RESET.
303 000000F8 EA000020 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
304 000000FC
305 000000FC
306 000000FC ;*******************************************************
*************************************************
307 000000FC ; UNDEFINED INSTRUCTION E
XCEPTION HANDLER
308 000000FC ;
309 000000FC ; Register Usage: R0 Exception Type
310 000000FC ; R1
311 000000FC ; R2
312 000000FC ; R3 Return PC
313 000000FC ;*******************************************************
*************************************************
314 000000FC
315 000000FC AREA CODE, CODE, READONLY
316 000000FC CODE32
317 000000FC
318 000000FC OS_CPU_ARM_ExceptUndefInstrHndlr
319 000000FC ; LR offset to return from this exception: 0.
ARM Macro Assembler Page 9
320 000000FC E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
321 00000100 E1A0300E MOV R3, LR ; Save link registe
r.
322 00000104 E3A00001 MOV R0, #OS_CPU_ARM_EXCEPT_UNDEF_IN
STR
; Set exception ID
to OS_CPU_ARM_EXCEP
T_UNDEF_INSTR.
323 00000108 EA00001C B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
324 0000010C
325 0000010C
326 0000010C ;*******************************************************
*************************************************
327 0000010C ; SOFTWARE INTERRUPT EXC
EPTION HANDLER
328 0000010C ;
329 0000010C ; Register Usage: R0 Exception Type
330 0000010C ; R1
331 0000010C ; R2
332 0000010C ; R3 Return PC
333 0000010C ;*******************************************************
*************************************************
334 0000010C
335 0000010C AREA CODE, CODE, READONLY
336 0000010C CODE32
337 0000010C
338 0000010C OS_CPU_ARM_ExceptSwiHndlr
339 0000010C ; LR offset to return from this exception: 0.
340 0000010C E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
341 00000110 E1A0300E MOV R3, LR ; Save link registe
r.
342 00000114 E3A00002 MOV R0, #OS_CPU_ARM_EXCEPT_SWI ; Se
t exception ID to O
S_CPU_ARM_EXCEPT_SW
I.
343 00000118 EA000018 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
344 0000011C
345 0000011C
346 0000011C ;*******************************************************
*************************************************
347 0000011C ; PREFETCH ABORT EXCEP
TION HANDLER
348 0000011C ;
349 0000011C ; Register Usage: R0 Exception Type
350 0000011C ; R1
351 0000011C ; R2
352 0000011C ; R3 Return PC
353 0000011C ;*******************************************************
*************************************************
354 0000011C
355 0000011C AREA CODE, CODE, READONLY
356 0000011C CODE32
357 0000011C
ARM Macro Assembler Page 10
358 0000011C OS_CPU_ARM_ExceptPrefetchAbortHndlr
359 0000011C E24EE004 SUB LR, LR, #4 ; LR offset to retu
rn from this except
ion: -4.
360 00000120 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
361 00000124 E1A0300E MOV R3, LR ; Save link registe
r.
362 00000128 E3A00003 MOV R0, #OS_CPU_ARM_EXCEPT_PREFETCH
_ABORT
; Set exception ID
to OS_CPU_ARM_EXCEP
T_PREFETCH_ABORT.
363 0000012C EA000013 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
364 00000130
365 00000130
366 00000130 ;*******************************************************
*************************************************
367 00000130 ; DATA ABORT EXCEPTI
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