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📄 dsp_test_m.mdl

📁 SVPWM应用
💻 MDL
📖 第 1 页 / 共 2 页
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	Block {
	  BlockType		  Mux
	  Name			  "Mux1"
	  Ports			  [2, 1]
	  Position		  [120, 61, 125, 119]
	  ShowName		  off
	  Inputs		  "2"
	  DisplayOption		  "bar"
	}
	Block {
	  BlockType		  Mux
	  Name			  "Mux2"
	  Ports			  [6, 1]
	  Position		  [780, 15, 785, 170]
	  ShowName		  off
	  Inputs		  "6"
	  DisplayOption		  "none"
	}
	Block {
	  BlockType		  DiscretePulseGenerator
	  Name			  "Pulse\nGenerator"
	  Position		  [150, 46, 175, 64]
	  ShowName		  off
	  PulseType		  "Time-based"
	  Amplitude		  "1"
	  Period		  "5e-4"
	  PulseWidth		  "50"
	  PhaseDelay		  "0"
	  SampleTime		  "1"
	  VectorParams1D	  on
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sample\nand Hold"
	  Ports			  [1, 1, 0, 1]
	  Position		  [185, 75, 220, 105]
	  ShowName		  off
	  SourceBlock		  "dspsigops/Sample\nand Hold"
	  SourceType		  "Sample and Hold"
	  trig			  "Rising edge"
	  initCond		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Pulses"
	  Position		  [805, 88, 835, 102]
	  Port			  "1"
	  OutputWhenDisabled	  "held"
	  InitialOutput		  "0"
	}
	Line {
	  SrcBlock		  "Demux2"
	  SrcPort		  3
	  Points		  [110, 0; 0, -20]
	  DstBlock		  "Mux"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "Demux2"
	  SrcPort		  2
	  Points		  [80, 0; 0, -25]
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Demux2"
	  SrcPort		  1
	  Points		  [60, 0; 0, -30]
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sample\nand Hold"
	  SrcPort		  1
	  DstBlock		  "Demux2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux1"
	  SrcPort		  1
	  DstBlock		  "Sample\nand Hold"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Discrete\nVirtual PLL"
	  SrcPort		  3
	  DstBlock		  "Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Pulse\nGenerator"
	  SrcPort		  1
	  Points		  [20, 0]
	  DstBlock		  "Sample\nand Hold"
	  DstPort		  trigger
	}
	Line {
	  SrcBlock		  "MATLAB Fcn"
	  SrcPort		  1
	  DstBlock		  "Demux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Clock"
	  SrcPort		  1
	  Points		  [35, 0]
	  DstBlock		  "Mux"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "Discrete\nVirtual PLL"
	  SrcPort		  2
	  DstBlock		  "Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "MATLAB Fcn"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Discrete\nVirtual PLL"
	  SrcPort		  1
	  Points		  [0, -10]
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Demux1"
	  SrcPort		  1
	  Points		  [5, 0; 0, -25; 70, 0]
	  Branch {
	    DstBlock		    "Mux2"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Data Type \nConversion"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Demux1"
	  SrcPort		  2
	  Points		  [55, 0; 0, 15; 10, 0]
	  Branch {
	    DstBlock		    "Mux2"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Data Type \nConversion4"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Demux1"
	  SrcPort		  3
	  Points		  [5, 0; 0, 40; 50, 0; 0, 15; 5, 0]
	  Branch {
	    DstBlock		    "Mux2"
	    DstPort		    5
	  }
	  Branch {
	    Points		    [0, 25]
	    DstBlock		    "Data Type \nConversion5"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Mux2"
	  SrcPort		  1
	  DstBlock		  "Pulses"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Data Type \nConversion"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Data Type \nConversion1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Data Type \nConversion1"
	  SrcPort		  1
	  DstBlock		  "Mux2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator1"
	  SrcPort		  1
	  DstBlock		  "Data Type \nConversion2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Data Type \nConversion2"
	  SrcPort		  1
	  DstBlock		  "Mux2"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "Logical\nOperator2"
	  SrcPort		  1
	  DstBlock		  "Data Type \nConversion3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Data Type \nConversion3"
	  SrcPort		  1
	  DstBlock		  "Mux2"
	  DstPort		  6
	}
	Line {
	  SrcBlock		  "Data Type \nConversion4"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Data Type \nConversion5"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Scope
      Name		      "Scope1"
      Ports		      [1]
      Position		      [380, 150, 415, 190]
      BackgroundColor	      "green"
      NamePlacement	      "alternate"
      Floating		      off
      Location		      [529, 353, 793, 677]
      Open		      off
      NumInputPorts	      "1"
      TickLabels	      "OneTimeTick"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
      }
      Grid		      "on"
      TimeRange		      "0.03"
      YMin		      "-500"
      YMax		      "500"
      SaveToWorkspace	      on
      SaveName		      "V_scope1"
      DataFormat	      "StructureWithTime"
      LimitDataPoints	      off
      MaxDataPoints	      "5000"
      Decimation	      "20"
      SampleInput	      off
      SampleTime	      "5e-6"
    }
    Block {
      BlockType		      SubSystem
      Name		      "SubSystem1"
      Ports		      []
      Position		      [428, 142, 521, 186]
      DropShadow	      on
      ShowName		      off
      OpenFcn		      "psbfft_scope(V_scope1,50,500,2,1);"
      ShowPortLabels	      on
      TreatAsAtomicUnit	      off
      RTWSystemCode	      "Auto"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      MaskDisplay	      "disp('Double click\\nto display spectrum\\nof V"
"ab load')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"SubSystem1"
	Location		[382, 92, 1015, 343]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Annotation {
	  Position		  [317, 116]
	  Text			  "Double clicking on this block will perform "
"the spectral analysis of a signal stored in a \"Structure with time\"\nThe an"
"alysis is performed by the \"psbfft_scope\" function.\n\nType  \"help psbfft_"
"scope\"  to obtain the function syntax and documentation.\n\nThe  callback to"
" \"psbfft_scope\" is stored in the \"Open function\" field of the Block Prope"
"rties. \n"
	  FontSize		  12
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Vdc1"
      Tag		      "PoWeRsYsTeMbLoCk"
      Description	      "source block"
      Ports		      [1, 1]
      Position		      [115, 25, 135, 60]
      Orientation	      "up"
      NamePlacement	      "alternate"
      SourceBlock	      "powerlib2/Electrical\nSources/DC Voltage Source"
      SourceType	      "DC Voltage Source"
      V			      "530"
      mesure		      "None"
      PSBOutputType	      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Voltage Measurement"
      Tag		      "PoWeRsYsTeMmEaSuReMeNt"
      Ports		      [2, 1]
      Position		      [310, 158, 335, 182]
      SourceBlock	      "powerlib2/Measurements/Voltage Measurement"
      SourceType	      "Voltage Measurement"
      PSBOutputType	      "0"
      PSBequivalent	      "1"
    }
    Line {
      SrcBlock		      "SVPWM Generator"
      SrcPort		      1
      DstBlock		      "IGBT Inverter1"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Voltage Measurement"
      SrcPort		      1
      DstBlock		      "Scope1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Bus Bar (thin horiz)1"
      SrcPort		      1
      DstBlock		      "Vdc1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Bus Bar (thin horiz)1"
      SrcPort		      2
      Points		      [15, 0]
      DstBlock		      "IGBT Inverter1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Vdc1"
      SrcPort		      1
      Points		      [40, 0]
      DstBlock		      "IGBT Inverter1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "3- Phase Series RLC "
      SrcPort		      1
      DstBlock		      "Bus Bar (vert)"
      DstPort		      1
    }
    Line {
      SrcBlock		      "3- Phase Series RLC "
      SrcPort		      2
      DstBlock		      "Bus Bar (vert)"
      DstPort		      2
    }
    Line {
      SrcBlock		      "3- Phase Series RLC "
      SrcPort		      3
      DstBlock		      "Bus Bar (vert)"
      DstPort		      3
    }
    Line {
      SrcBlock		      "IGBT Inverter1"
      SrcPort		      1
      Points		      [0, 0; 15, 0]
      Branch {
	DstBlock		"3- Phase Series RLC "
	DstPort			1
      }
      Branch {
	Points			[0, 85; 30, 0]
	DstBlock		"Voltage Measurement"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "IGBT Inverter1"
      SrcPort		      2
      Points		      [5, 0; 0, -5]
      DstBlock		      "3- Phase Series RLC "
      DstPort		      2
    }
    Line {
      SrcBlock		      "IGBT Inverter1"
      SrcPort		      3
      Points		      [0, 0]
      Branch {
	Points			[5, 0; 0, -10]
	DstBlock		"3- Phase Series RLC "
	DstPort			3
      }
      Branch {
	Points			[0, 65]
	DstBlock		"Voltage Measurement"
	DstPort			2
      }
    }
  }
}

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