📄 dsp_test_m.mdl
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Model {
Name "DSP_TEST_M"
Version 4.00
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ShowPortDataTypes off
ShowStorageClass off
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CovPath "/"
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CovMetricSettings "dw"
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BlockParametersDataTip off
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ToolBar on
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BrowserLookUnderMasks off
InitFcn "powericon('psbinitsys',bdroot);"
Created "Sun Oct 05 21:28:25 2003"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "李洁"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sat Oct 25 17:19:02 2003"
ModelVersionFormat "1.%<AutoIncrement:51>"
ConfigurationManager "None"
SimParamPage "Solver"
StartTime "0.0"
StopTime "1"
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Solver "FixedStepDiscrete"
RelTol "1e-3"
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Refine "1"
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "5e-7"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
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ExternalInput "[t, u]"
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Block {
BlockType Reference
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SourceType "3-phase RLC series element"
R "20000"
L "0"
C "inf"
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Block {
BlockType Reference
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Orientation "up"
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SourceBlock "powerlib2/Connectors/Bus Bar (thin horiz)"
SourceType "Bus Bar"
input "0"
output "2"
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Block {
BlockType Reference
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SourceType "PSB option block system"
methode "off"
Ts "5e-7"
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Block {
BlockType Reference
Name "IGBT Inverter1"
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NamePlacement "alternate"
SourceBlock "powerlib2/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
arms "3"
confi "ABC as output terminals"
injcc "1000"
cf "inf"
device "IGBT / Diodes"
Ron "1e-3"
Lon "0"
VFs "[ 0.8 0.8 ]"
Vf ".8"
gtoparameters "[ 1e-6 , 1e-6 ]"
igbtparameters "[ 1e-5, 2e-5]"
mesure "None"
PSBOutputType "111"
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Block {
BlockType SubSystem
Name "SVPWM Generator"
Ports [0, 1]
Position [45, 80, 85, 140]
ForegroundColor "orange"
BackgroundColor "lightBlue"
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
MaskType "SVPWM发生器"
MaskPromptString "频率（Hz）"
MaskStyleString "edit"
MaskTunableValueString "on"
MaskEnableString "on"
MaskVisibilityString "on"
MaskToolTipString "on"
MaskVariables "Freq=@1;"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "50"
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Name "Data Type \nConversion5"
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Block {
BlockType Demux
Name "Demux1"
Ports [1, 3]
Position [540, 46, 545, 84]
BackgroundColor "black"
ShowName off
Outputs "3"
BusSelectionMode off
}
Block {
BlockType Demux
Name "Demux2"
Ports [1, 3]
Position [245, 71, 250, 109]
BackgroundColor "black"
ShowName off
Outputs "3"
BusSelectionMode off
}
Block {
BlockType Reference
Name "Discrete\nVirtual PLL"
Ports [0, 3]
Position [25, 26, 90, 124]
SourceBlock "powerlib_extras/Discrete \nControl Blocks/D"
"iscrete\nVirtual PLL"
SourceType "Discrete Virtual PLL"
Freq "Freq"
Phase "0"
Ts "5e-7"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [1, 1]
Position [675, 45, 705, 65]
ShowName off
Operator "NOT"
Inputs "2"
}
Block {
BlockType Logic
Name "Logical\nOperator1"
Ports [1, 1]
Position [670, 95, 700, 115]
ShowName off
Operator "NOT"
Inputs "2"
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Block {
BlockType Logic
Name "Logical\nOperator2"
Ports [1, 1]
Position [670, 145, 700, 165]
ShowName off
Operator "NOT"
Inputs "2"
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn"
Position [460, 50, 520, 80]
MATLABFcn "SVPWM_sim(u(1),u(2),u(3),u(4),u(5))"
OutputDimensions "-1"
OutputSignalType "auto"
Output1D off
}
Block {
BlockType Mux
Name "Mux"
Ports [5, 1]
Position [395, 31, 400, 99]
ShowName off
Inputs "5"
DisplayOption "bar"
}
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