head.s

在阳初s3c2410上实现的uudecode协议

@
@ Start of executable code 
@

#include "config.h"

.global _start

_start:
@ Exception vector table (physical address = 0x00000000)
	b	reset
	b	.
  	b	.
	b	.
	b	.
	b	.
	b	.
	b	.


@ Start VIVI head
reset:
@ disable watch dog timer
	ldr		r1, =WTCON
	ldr		r2, =0x0
	str		r2, [r1]

@ disable all interrupts
	ldr		r1, =INTMSK
	ldr		r2, =0xffffffff
	str		r2, [r1]
	ldr 	r1, =INTSUBMSK
	ldr		r2, =0x7ff
	str		r2, [r1]
	
@ initialise system clocks
	ldr		r1, =LOCKTIME
	ldr		r2, =((U_LTIME<<12)+M_LTIME)
	str		r2, [r1]

	ldr		r1, =CLKDIVN
	ldr		r2, =((H_DIVN1<<2)+(H_DIVN<<1)+P_DIVN)
	str		r2, [r1]

	mrc		p15, 0, r1, c1, c0, 0	@ read ctrl register 
	orr		r1, r1, #0xc0000000		@ Asynchronous  
	mcr		p15, 0, r1, c1, c0, 0	@ write ctrl register
	
	@ usb clock is 48Mhz
	ldr 	r0, =UPLLCON  @ Fin=12MHz, Fout=48MHz
	ldr 	r1, =((U_LMDIV<<12)+(U_LPDIV<<4)+U_LSDIV) 
	str 	r1, [r0]
 
 	nop
 	nop
 	nop
 	nop
 	ldr 	r0, =UPLLCON  @ Fin=12MHz, Fout=48MHz
	ldr 	r1, =((U_LMDIV<<12)+(U_LPDIV<<4)+U_LSDIV)
	str 	r1, [r0]

	@ CPU clock is 200 Mhz
	ldr		r1, =MPLLCON
	ldr		r2, =((M_LMDIV<<12)+(M_LPDIV<<4)+M_LSDIV)
	str		r2, [r1]
	
@ set memory control registers
	ldr		r1, =BWSCON
	adrl	r2, mem_cfg_val
	add		r3, r1, #52
1:	ldr		r4, [r2], #4
	str		r4, [r1], #4
	cmp		r1, r3
	bne		1b

@ turn to _main function by c	
	ldr 	sp, =0x00001000
	bl		main

@ if main return die here
die:
	b die


@
@ Data Area
@
@ Memory configuration values
.align 4
mem_cfg_val:
	.long	((B7_ST<<31)+(B7_WS<<30)+(B7_DW<<28)+(B6_ST<<27)+(B6_WS<<26)+(B6_DW<<24)+(B5_ST<<23)+(B5_WS<<22)+(B5_DW<<20)+(B4_ST<<19)+(B4_WS<<18)+(B4_DW<<16)+(B3_ST<<15)+(B3_WS<<14)+(B3_DW<<12)+(B2_ST<<11)+(B2_WS<<10)+(B2_DW<<8)+(B1_ST<<7)+(B1_WS<<6)+(B1_DW<<4)+(B0_DW<<1))
	.long	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tcah<<4)+(B0_Tacp<<2)+B0_PMC)
	.long	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tcah<<4)+(B1_Tacp<<2)+B1_PMC)
	.long	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tcah<<4)+(B2_Tacp<<2)+B2_PMC)
	.long	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tcah<<4)+(B3_Tacp<<2)+B3_PMC)
	.long	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tcah<<4)+(B4_Tacp<<2)+B4_PMC)
	.long	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tcah<<4)+(B5_Tacp<<2)+B5_PMC)
	.long	((B6_MT<<15)+(B6_Trcd<<2)+B6_SCAN)
	.long	((B7_MT<<15)+(B7_Trcd<<2)+B7_SCAN)
	.long	((REF_REFEN<<23)+(REF_TREFMD<<22)+(REF_Trp<<20)+(REF_Tsrc<<18)+REF_REFCNT)
	.long	((BS_BURST_EN<<7)+(BS_SCKE_EN<<5)+(BS_SCLK_EN<<4)+BS_BK76MAP)
	.long	((MB6_WBL<<9)+(MB6_TM<<7)+(MB6_CL<<4)+(MB6_BT<<3)+MB6_BL)
	.long	((MB7_WBL<<9)+(MB7_TM<<7)+(MB7_CL<<4)+(MB7_BT<<3)+MB7_BL)