board.h

在阳初s3c2410开发板上实现的xmodem传输协议

#ifndef __BOARD_H__
#define __BOARD_H__

#include "s3c2410.h"

/* lock time value */
#define U_LTIME	  	0xfff
#define M_LTIME	  	0xfff

/* clock divider control value */
#define H_DIVN1   	0x0
#define H_DIVN    	0x1
#define P_DIVN    	0x1

/* UPLL control value */
#define U_LMDIV	 	0x78
#define U_LPDIV	 	0x02
#define U_LSDIV	 	0x03

/* MPLL control value */
#define M_LMDIV	 	0xa1
#define M_LPDIV	 	0x03
#define M_LSDIV	 	0x01

/* bank0 controller */
#define B0_DW		0x0

#define B0_Tacs 	0x0
#define B0_Tcos 	0x0
#define B0_Tacc 	0x7
#define B0_Tcoh 	0x0
#define B0_Tcah 	0x0
#define B0_Tacp 	0x0
#define B0_PMC  	0x0

/* bank1 controller */
#define B1_ST		0x0
#define B1_WS		0x0
#define B1_DW		0x1

#define B1_Tacs 	0x0
#define B1_Tcos 	0x0
#define B1_Tacc 	0x7
#define B1_Tcoh 	0x0
#define B1_Tcah 	0x0
#define B1_Tacp 	0x0
#define B1_PMC  	0x0

/* bank2 controller */
#define B2_ST		0x0
#define B2_WS		0x0
#define B2_DW		0x1

#define B2_Tacs 	0x0
#define B2_Tcos 	0x0
#define B2_Tacc 	0x7
#define B2_Tcoh 	0x0
#define B2_Tcah 	0x0
#define B2_Tacp 	0x0
#define B2_PMC  	0x0

/* bank3 controller */
#define B3_ST		0x1
#define B3_WS		0x1
#define B3_DW		0x3

#define B3_Tacs 	0x0
#define B3_Tcos 	0x3
#define B3_Tacc 	0x7
#define B3_Tcoh 	0x1
#define B3_Tcah 	0x0
#define B3_Tacp 	0x3
#define B3_PMC  	0x0

/* bank4 controller */
#define B4_ST		0x0
#define B4_WS		0x0
#define B4_DW		0x1

#define B4_Tacs 	0x0
#define B4_Tcos 	0x0
#define B4_Tacc 	0x7
#define B4_Tcoh 	0x0
#define B4_Tcah 	0x0
#define B4_Tacp 	0x0
#define B4_PMC  	0x0

/* bank5 controller */
#define B5_ST		0x0
#define B5_WS		0x0
#define B5_DW		0x1

#define B5_Tacs 	0x0
#define B5_Tcos 	0x0
#define B5_Tacc 	0x7
#define B5_Tcoh 	0x0
#define B5_Tcah 	0x0
#define B5_Tacp 	0x0
#define B5_PMC  	0x0

/* bank6 controller */
#define B6_ST		0x0
#define B6_WS		0x0
#define B6_DW		0x2

#define B6_MT   	0x3
#define B6_Trcd 	0x1
#define B6_SCAN 	0x1

/* bank7 controller */
#define B7_ST		0x0
#define B7_WS		0x0
#define B7_DW		0x2

#define B7_MT   	0x3
#define B7_Trcd 	0x1
#define B7_SCAN 	0x1

/* refresh controller*/
#define REF_REFEN  	0x1
#define REF_TREFMD 	0x0
#define REF_Trp    	0x0
#define REF_Tsrc   	0x3
#define REF_REFCNT 	0x459

/* bank size controller */
#define BS_BURST_EN 0x1
#define BS_SCKE_EN  0x1
#define BS_SCLK_EN  0x1
#define BS_BK76MAP  0x2

/* SDRAM mode set */
#define MB6_WBL		0x0
#define MB6_TM		0x0
#define MB6_CL		0x3
#define MB6_BT		0x0
#define MB6_BL		0x0

/* SDRAM mode set */
#define MB7_WBL		0x0
#define MB7_TM		0x0
#define MB7_CL		0x3
#define MB7_BT		0x0
#define MB7_BL		0x0

/* SDRAM base address */
#define SDRAM_BASE	0x30000000
#define SDRAM_END	0x33FFFFFC

#endif /* __BOARD_H__ */