cs8900dbg.c

支持三星原产的S3C2413开发板

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/******************************************************************************
 *
 * System On Chip(SOC)
 *
 * Copyright (c) 2002 Software Center, Samsung Electronics, Inc.
 * All rights reserved.
 *
 * This software is the confidential and proprietary information of Samsung 
 * Electronics, Inc("Confidential Information"). You Shall not disclose such 
 * Confidential Information and shall use it only in accordance with the terms 
 * of the license agreement you entered into Samsung.
 *      
 ******************************************************************************
*/
    
#include <windows.h>
#include <halether.h>
#include "cs8900dbg.h"
#include "bsp_cfg.h"

// Hash creation constants.
//
#define CRC_PRIME               0xFFFFFFFF;
#define CRC_POLYNOMIAL          0x04C11DB6;

/******************************************************************************/
/*  For SMDK2413 
  * in SMDK2413, For CS8900 16-bit interface, 
  * the A1 address value has to be tied to CS8900 A0 pin(A2->A0 for 32bit interface).
  * so, the offset value(include I/O select address) has to be left-shift 1.;
  * This file is from \PUBLIC\COMMON\OAK\DRIVERS\ETHDBG\CS8900\cs8900dbg.c
*/

#if (BSP_SMDK2413==1 && !SMDK2413_REV14)

//#ifdef SMDK2413_REV14
//#define IOREAD(o)					((USHORT)*((volatile USHORT *)(dwEthernetIOBase + (o))))
//#define IOWRITE(o, d)				*((volatile USHORT*)(dwEthernetIOBase + (o))) = (USHORT)(d)
//#define MEMREAD(o)					((USHORT)*((volatile USHORT *)(dwEthernetMemBase + (o))))
//#define MEMWRITE(o, d)				*((volatile USHORT *)(dwEthernetMemBase + (o))) = (USHORT)(d)
//#else
#define IOREAD(o)					((USHORT)*((volatile USHORT *)(dwEthernetIOBase + ((o)<<1) )))
#define IOWRITE(o, d)				*((volatile USHORT *)(dwEthernetIOBase + ((o)<<1))) = (USHORT)(d)
#define MEMREAD(o)					((USHORT)*((volatile USHORT *)(dwEthernetMemBase + ((o)<<1))))
#define MEMWRITE(o, d)				*((volatile USHORT *)(dwEthernetMemBase + ((o)<<1))) = (USHORT)(d)
//#endif

#else
#define IOREAD(o)					((USHORT)*((volatile USHORT *)(dwEthernetIOBase + (o))))
#define IOWRITE(o, d)				*((volatile USHORT *)(dwEthernetIOBase + (o))) = (USHORT)(d)

#define MEMREAD(o)					((USHORT)*((volatile USHORT *)(dwEthernetMemBase + (o))))
#define MEMWRITE(o, d)				*((volatile USHORT *)(dwEthernetMemBase + (o))) = (USHORT)(d)
#endif

#define MAX_COUNT					0x100000

#define CS8900DBG_PROBE				(1 << 0)

static DWORD dwEthernetIOBase;
static DWORD dwEthernetMemBase;

#define CS8900_MEM_MODE

#ifdef	CS8900_MEM_MODE

#define READ_REG1					ReadReg
#define READ_REG2					MEMREAD

#define WRITE_REG1					WriteReg
#define WRITE_REG2					MEMWRITE

#else

#define READ_REG1					ReadReg
#define READ_REG2					ReadReg

#define WRITE_REG1					WriteReg
#define WRITE_REG2					WriteReg

#endif

static	BOOL bIsPacket;


static USHORT 
ReadReg(USHORT offset)
{
	//RETAILMSG(1, (TEXT("dbg:ReadReg%x, offset:%x\n"), dwEthernetIOBase, offset));
	IOWRITE(IO_PACKET_PAGE_POINTER, offset);
	return IOREAD(IO_PACKET_PAGE_DATA_0);
}

static void 
WriteReg(USHORT offset, USHORT data)
{
	//RETAILMSG(1, (TEXT(":offset:%x, data:%x\n"),  offset, data));
	IOWRITE(IO_PACKET_PAGE_POINTER, offset);
	IOWRITE(IO_PACKET_PAGE_DATA_0 , data);
}


/*
    @func   BYTE | CalculateHashIndex | Computes the logical addres filter hash index value.  This used when there are multiple
	                                    destination addresses to be filtered.
    @rdesc  Hash index value.
    @comm    
    @xref   
*/
BYTE CalculateHashIndex( BYTE  *pMulticastAddr )
{
   DWORD CRC;
   BYTE  HashIndex;
   BYTE  AddrByte;
   DWORD HighBit;
   int   Byte;
   int   Bit;

   // Prime the CRC.
   CRC = CRC_PRIME;

   // For each of the six bytes of the multicast address.
   for ( Byte=0; Byte<6; Byte++ )
   {
      AddrByte = *pMulticastAddr++;

      // For each bit of the byte.
      for ( Bit=8; Bit>0; Bit-- )
      {
         HighBit = CRC >> 31;
         CRC <<= 1;

         if ( HighBit ^ (AddrByte & 1) )
         {
            CRC ^= CRC_POLYNOMIAL;
            CRC |= 1;
         }

         AddrByte >>= 1;
      }
   }

   // Take the least significant six bits of the CRC and copy them
   // to the HashIndex in reverse order.
   for( Bit=0,HashIndex=0; Bit<6; Bit++ )
   {
      HashIndex <<= 1;
      HashIndex |= (BYTE)(CRC & 1);
      CRC >>= 1;
   }

   return(HashIndex);
}


static BOOL Probe(void)
{
	BOOL r = FALSE;

	do 
	{
		/* Check the EISA registration number.	*/
		if (READ_REG1(PKTPG_EISA_NUMBER) != CS8900_EISA_NUMBER)
		{
			RETAILMSG(1, (TEXT("ERROR: Probe: EISA Number Error.\r\n")));
			break;
		}
		/* Check the Product ID.				*/
		if ((READ_REG1(PKTPG_PRDCT_ID_CODE) & CS8900_PRDCT_ID_MASK)
			!= CS8900_PRDCT_ID)
		{
			RETAILMSG(1, (TEXT("ERROR: Probe: Product ID Error.\r\n")));
			break;
		}
	   
		RETAILMSG(1, (TEXT("INFO: Probe: CS8900 is detected.\r\n")));
		r = TRUE;
	} while (0);

	return r;
}

static BOOL 
Reset(void)
{
	BOOL r = FALSE;
	USHORT dummy;
	int i;
											/* Set RESET bit of SelfCTL register.	*/
	do 
	{
		//WRITE_REG1(PKTPG_SELF_CTL, SELF_CTL_RESET | SELF_CTL_LOW_BITS);
		WRITE_REG1(PKTPG_SELF_CTL, SELF_CTL_RESET);

								/* Wait until INITD bit of SelfST register is set.	*/
		for (i = 0; i < MAX_COUNT; i++)
		{
			dummy = READ_REG1(PKTPG_SELF_ST);
			if (dummy & SELF_ST_INITD) break;
			//dongo
			else RETAILMSG(1, (TEXT("Status read:%x.\r\n"), dummy));
			
		}

		if (i >= MAX_COUNT)
		{
			RETAILMSG(1, (TEXT("ERROR: Reset: Reset failed (SelfST).\r\n")));
			break;
		}

						/* Wait until SIBUSY bit of SelfST register is cleared.		*/
		for (i = 0; i < MAX_COUNT; i++)
		{
			dummy = READ_REG1(PKTPG_SELF_ST);
			if ((dummy & SELF_ST_SIBUSY) == 0) break;
		}

		if (i >= MAX_COUNT)
		{
			RETAILMSG(1, (TEXT("ERROR: Reset: Reset failed (SIBUSY).\r\n")));
			break;
		}
		r = TRUE;

	} while (0);

	return r;
}


void CS8900DBG_EnableInts(void)
{
	USHORT temp;
						/* If INTERRUPT_NUMBER is 0,							*/
						/*	Interrupt request will be generated from INTRQ0 pin */
	WRITE_REG2(PKTPG_INTERRUPT_NUMBER, INTERRUPT_NUMBER);
	temp = READ_REG2(PKTPG_BUS_CTL) | BUS_CTL_ENABLE_IRQ;
	WRITE_REG2(PKTPG_BUS_CTL, temp);
}


void CS8900DBG_DisableInts(void)
{
	USHORT temp;

	temp = READ_REG2(PKTPG_BUS_CTL) & ~BUS_CTL_ENABLE_IRQ;
	WRITE_REG2(PKTPG_BUS_CTL, temp);
}


static BOOL 
Init(USHORT *mac)
{
	USHORT temp;

#ifdef CS8900_MEM_MODE

	WRITE_REG1(PKTPG_MEMORY_BASE_ADDR     , (USHORT)(dwEthernetMemBase & 0xffff));
	WRITE_REG1(PKTPG_MEMORY_BASE_ADDR + 2 , (USHORT)(dwEthernetMemBase >> 16   ));
	WRITE_REG1(PKTPG_BUS_CTL              ,  BUS_CTL_MEMORY_E | BUS_CTL_LOW_BITS);

#endif

	temp = READ_REG2(PKTPG_LINE_CTL) | LINE_CTL_10_BASE_T | LINE_CTL_MOD_BACKOFF;
	WRITE_REG2(PKTPG_LINE_CTL, temp);
						
	WRITE_REG2(PKTPG_RX_CFG, RX_CFG_RX_OK_I_E | RX_CFG_LOW_BITS);

	WRITE_REG2(PKTPG_INDIVISUAL_ADDR + 0, *mac++);
	WRITE_REG2(PKTPG_INDIVISUAL_ADDR + 2, *mac++);
	WRITE_REG2(PKTPG_INDIVISUAL_ADDR + 4, *mac  );

	WRITE_REG2(PKTPG_RX_CTL, (RX_CTL_RX_OK_A | RX_CTL_IND_ADDR_A | RX_CTL_BROADCAST_A | RX_CTL_LOW_BITS));

	WRITE_REG2(PKTPG_TX_CFG, TX_CFG_LOW_BITS);

	temp = READ_REG2(PKTPG_LINE_CTL) | LINE_CTL_RX_ON | LINE_CTL_TX_ON;
	WRITE_REG2(PKTPG_LINE_CTL,temp);

	RETAILMSG(1, (TEXT("INFO: Init: CS8900_Init OK.\r\n")));
	return TRUE;
}

static int
RcvPkt(BYTE *pbData, DWORD dwLength)
{
					/* use int rather than short for the reason of performance	*/
	DWORD   length;
	DWORD   rlen = 0;