📄 startup.s
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and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1
subs r0, r0, #1
bne %b30
ldr r0, =vGPIOBASE
str r2, [r0, #oGSTATUS3]
[{FALSE}
ldr r0, =vGPIOBASE
ldr r1, =0x550a
str r1, [r0, #oGPFCON]
ldr r1, =0x30
str r1, [r0, #oGPFDAT]
]
; 4. Interrupt Disable
; ldr r0, =vINTBASE
; mvn r2, #0
; str r2, [r0, #oINTMSK]
; str r2, [r0, #oSRCPND]
; str r2, [r0, #oINTPND]
;; 5. Cache Flush
bl OALClearUTLB
bl OALFlushICache
ldr r0, = (DCACHE_LINES_PER_SET - 1)
ldr r1, = (DCACHE_NUM_SETS - 1)
ldr r2, = DCACHE_SET_INDEX_BIT
ldr r3, = DCACHE_LINE_SIZE
bl OALFlushDCache
; 6. Setting unmask Wakeup External Interrupt(EINT0)
; ldr r0, =vINTMSK
; ldr r1, =0xfffffffe
; str r1, [r0]
; ldr r0,=vEINTMASK
; ldr r1, =0xfffffffe
; str r1, [r0]
; 7. Getting into Sleep mode
ldr r6,=vADCCON
ldr r7,[r6]
orr r7,r7,#(1<<2)
str r7,[r6]
ldr r0, =vPWRCFG
mov r1, #((0x3<<6))
str r1, [r0]
mov r0,#0x0
mcr p15,0,r0,c7,c0,4
b .
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Sometimes it is not working in cache mode. So I modify to jump to ROM area.
;
;;; ldr r6, =0x92000000 ; make address to 0x9200 0020
;;; add r6, r6, #0x20 ;
;;; mov pc, r6 ; jump to Power off code in ROM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN 32 ; for I-Cache Line(32Byte, 8 Word)
;;; LTORG
; This point is called from EBOOT's startup code(MMU is enabled)
; in this routine, left information(REGs, INTMSK, INTSUBMSK ...)
Awake_address
; 1. Recover CPU Registers
ldr r3, =SLEEPDATA_BASE_VIRTUAL ; Sleep mode information data structure
add r2, r3, #SleepState_FIQ_SPSR
mov r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Enter FIQ mode, no interrupts - also FIQ
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
ldr r8, [r2], #4
ldr r9, [r2], #4
ldr r10, [r2], #4
ldr r11, [r2], #4
ldr r12, [r2], #4
ldr sp, [r2], #4
ldr lr, [r2], #4
mov r1, #Mode_ABT:OR:I_Bit ; Enter ABT mode, no interrupts
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
ldr sp, [r2], #4
ldr lr, [r2], #4
mov r1, #Mode_IRQ:OR:I_Bit ; Enter IRQ mode, no interrupts
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
ldr sp, [r2], #4
ldr lr, [r2], #4
mov r1, #Mode_UND:OR:I_Bit ; Enter UND mode, no interrupts
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
ldr sp, [r2], #4
ldr lr, [r2], #4
mov r1, #Mode_SYS:OR:I_Bit ; Enter SYS mode, no interrupts
msr cpsr, r1
ldr sp, [r2], #4
ldr lr, [r2]
mov r1, #Mode_SVC:OR:I_Bit ; Enter SVC mode, no interrupts - FIQ is available
msr cpsr, r1
ldr r0, [r3, #SleepState_SVC_SPSR]
msr spsr, r0
; 2. Recover Last mode's REG's, & go back to caller of OALCPUPowerOff()
ldr sp, [r3, #SleepState_SVC_SP]
ldr lr, [sp], #4
ldmia sp!, {r4-r12}
mov pc, lr ; and now back to our sponsors
;---------------------------------------------------------------------------------------------------
; memoy init function.
LTORG
MEMDATA DATA
DCD ((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<2)+(BW<<0))
DCD ((BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4) + (1<<28) + (1<<26))
DCD ((tRAS<<20)+(tRC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
DCD ((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))
InitMEM
;Set SDR Memory parameter control registers
;adr r0, =MEMDATA
add r0, pc, #MEMDATA - (. + 8)
ldr r1,=BANKCFG ;
add r2, r0, #16 ;End address of MEMDATA
110
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B110
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x1<<0) ; 4nd : Issue a PALL command
str r1,[r2]
ldr r4,=REFRESH ; 5fh : refresh cycle every 255-clock cycles
ldr r0,=0xff
str r0,[r4]
mov r0, #0x100 ; 6th : wait 2 auto - clk
120 subs r0, r0,#1;
bne %B120
bic r1,r1,#(0x3<<0) ; 7th : Issue a MRS command
orr r1,r1,#(0x2<<0)
str r1,[r2]
ldr r4,=REFRESH ; 8fh : refresh normal
ldr r0,=REFCYC
str r0,[r4]
orr r1,r1,#(0x3<<0) ; 9th : Issue a EMRS command
str r1,[r2]
bic r1,r1,#(0x3<<0) ; 10th : Issue a Normal mode
str r1,[r2]
mov pc, lr
InitSSMC
;Set SSMC Memory parameter control registers : AMD Flash
ldr r0,=SMBIDCYR0
ldr r1,=IDCY0
str r1,[r0]
ldr r0,=SMBWSTRDR0
ldr r1,=WSTRD0
str r1,[r0]
ldr r0,=SMBWSTWRR0
ldr r1,=WSTWR0
str r1,[r0]
ldr r0,=SMBWSTOENR0
ldr r1,=WSTOEN0
str r1,[r0]
ldr r0,=SMBWSTWENR0
ldr r1,=WSTWEN0
str r1,[r0]
ldr r0,=SMBCR0
ldr r1,=(SMBCR0_2+SMBCR0_1+SMBCR0_0)
str r1,[r0]
ldr r0,=SMBWSTBRDR0
ldr r1,=WSTBRD0
str r1,[r0]
ldr r0,=SMBWSTBRDR0
ldr r1,=WSTBRD0
str r1,[r0]
ldr r0,=SSMCCR
ldr r1,=((MemClkRatio<<1)+(SMClockEn<<0))
str r1,[r0]
ldr r0,=SMBWSTRDR5
ldr r1,=0xe
str r1,[r0]
mov pc, lr
LTORG
;-------------------------------------------
; Delay routine.
DELAY_100
11
mov r10, #100
10 subs r10,r10,#0x1
bne %B10
subs r11, r11, #0x1
bne %B11
mov pc, lr
;-------------------------------------------
; Led display(Infinite) .
loop_led
LED_ON 0x3
ldr r0,=0x800000
10 subs r0, r0, #1
bne %B10
LED_ON 0xC
ldr r0,=0x800000
12 subs r0, r0, #1
bne %B12
b loop_led
vloop_led
VLED_ON 0xe
ldr r0,=0x80000
10 subs r0, r0, #1
bne %B10
VLED_ON 0xf
ldr r0,=0x80000
12 subs r0, r0, #1
bne %B12
b vloop_led ; Infinite loop
ENTRY_END
;------------------------------------------------------------------------------
; Clock Division Change funtion for DVS on S3C2413A.
;------------------------------------------------------------------------------
; HALFHCLK [5], DVS [4], ARMDIV [3], PCLKDIV [2], HCLKDIV [1:0]
LEAF_ENTRY CLKDIV124
ldr r0, = vCLKDIVN
ldr r1, [r0]
bic r1, r1, #(0x2F)
orr r1, r1, #(0x05) ; 1:2:4
str r1, [r0]
mov pc, lr
LEAF_ENTRY CLKDIV144
ldr r0, = vCLKDIVN
ldr r1, [r0]
bic r1, r1, #(0x2F)
orr r1, r1, #((0x0<<5) + (0x0<<3) + (0x0<<2) + (0x3)) ; 1:4:4
str r1, [r0]
mov pc, lr
LEAF_ENTRY DVS_ON
ldr r0, = vCLKDIVN
ldr r1, [r0]
orr r1, r1, #(0x1<<4) ; DVS bit = 1(FCLK = HCLK)
str r1, [r0]
mov pc, lr
LEAF_ENTRY DVS_OFF
ldr r0, = vCLKDIVN
ldr r1, [r0]
bic r1, r1, #(0x1<<4) ; DVS bit = 0(FCLK = MPLL clock)
str r1, [r0]
mov pc, lr
END
END
;------------------------------------------------------------------------------
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