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📄 startup.s

📁 支持三星原产的S3C2413开发板
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;
;  Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
;  Use of this source code is subject to the terms of the Microsoft end-user
;  license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
;  If you did not accept the terms of the EULA, you are not authorized to use
;  this source code. For a copy of the EULA, please see the LICENSE.RTF on your
;  install media.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Kernel startup routine for Samsung SMDK2413 board. Hardware is
;   initialized in boot loader - so there isn't much code at all.
;
;------------------------------------------------------------------------------

        INCLUDE kxarm.h
		INCLUDE s3c2413.inc

		IMPORT  OALClearUTLB
		IMPORT  OALFlushICache
		IMPORT  OALFlushDCache

; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS       EQU     2
DCACHE_LINES_PER_SET            EQU     4
DCACHE_NUM_SETS                 EQU     64
DCACHE_SET_INDEX_BIT            EQU     (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE                EQU     32




SLEEPDATA_BASE_VIRTUAL          EQU	0xA0028000		; keep in sync w/ config.bib
SLEEPDATA_BASE_PHYSICAL         EQU	0x30028000

SleepState_Data_Start		EQU     (0)

SleepState_WakeAddr    		EQU     (SleepState_Data_Start		    )
SleepState_MMUCTL           EQU     (SleepState_WakeAddr    + WORD_SIZE )
SleepState_MMUTTB       	EQU     (SleepState_MMUCTL  	+ WORD_SIZE )
SleepState_MMUDOMAIN    	EQU     (SleepState_MMUTTB  	+ WORD_SIZE )
SleepState_SVC_SP       	EQU     (SleepState_MMUDOMAIN   + WORD_SIZE )
SleepState_SVC_SPSR     	EQU     (SleepState_SVC_SP  	+ WORD_SIZE )
SleepState_FIQ_SPSR     	EQU     (SleepState_SVC_SPSR    + WORD_SIZE )
SleepState_FIQ_R8       	EQU     (SleepState_FIQ_SPSR    + WORD_SIZE )
SleepState_FIQ_R9       	EQU     (SleepState_FIQ_R8  	+ WORD_SIZE )
SleepState_FIQ_R10      	EQU     (SleepState_FIQ_R9  	+ WORD_SIZE )
SleepState_FIQ_R11      	EQU     (SleepState_FIQ_R10 	+ WORD_SIZE )
SleepState_FIQ_R12      	EQU     (SleepState_FIQ_R11 	+ WORD_SIZE )
SleepState_FIQ_SP       	EQU     (SleepState_FIQ_R12 	+ WORD_SIZE )
SleepState_FIQ_LR       	EQU     (SleepState_FIQ_SP  	+ WORD_SIZE )
SleepState_ABT_SPSR     	EQU     (SleepState_FIQ_LR  	+ WORD_SIZE )
SleepState_ABT_SP       	EQU     (SleepState_ABT_SPSR    + WORD_SIZE )
SleepState_ABT_LR       	EQU     (SleepState_ABT_SP  	+ WORD_SIZE )
SleepState_IRQ_SPSR     	EQU     (SleepState_ABT_LR  	+ WORD_SIZE )
SleepState_IRQ_SP       	EQU     (SleepState_IRQ_SPSR    + WORD_SIZE )
SleepState_IRQ_LR       	EQU     (SleepState_IRQ_SP  	+ WORD_SIZE )
SleepState_UND_SPSR     	EQU     (SleepState_IRQ_LR  	+ WORD_SIZE )
SleepState_UND_SP       	EQU     (SleepState_UND_SPSR    + WORD_SIZE )
SleepState_UND_LR       	EQU     (SleepState_UND_SP  	+ WORD_SIZE )
SleepState_SYS_SP       	EQU     (SleepState_UND_LR  	+ WORD_SIZE )
SleepState_SYS_LR       	EQU     (SleepState_SYS_SP  	+ WORD_SIZE )

SleepState_Data_End     	EQU     (SleepState_SYS_LR	+ WORD_SIZE )

SLEEPDATA_SIZE		    	EQU     ((SleepState_Data_End - SleepState_Data_Start) / 4)

 

;---------------------------------------------------------------------------
;
; Macro to feed the LED Reg (The GPIO) with the value desired for debugging.
; Uses physical address
;
; GPFDAT [7:4] is assigned to LEDs.

	MACRO
	LED_ON	$data

	LDR	r10, = GPFDN
	LDR	r11, = 0x00ff	;Pull-Down Disable
	STR	r11, [r10]
	
	LDR	r10, = GPFCON
	LDR	r11, = (0x5500)	; GPF[7:4] Output .
	STR	r11, [r10]
	LDR	r10, =GPFDAT
	LDR	r11, =$data
	MOV     r11, r11, lsl #4	; [7:4]
  	STR	r11, [r10]
  	MEND


; LED_ON using virtual address
;
	MACRO
	VLED_ON	$data
	
	LDR	r10, = vGPFDN
	LDR	r11, = 0x00ff	;Pull-Down Disable
	STR	r11, [r10]
	
	LDR	r10, = vGPFCON
	LDR	r11, = (0x5500)	; GPF[7:4] Output .
	STR	r11, [r10]
	LDR	r10, =vGPFDAT
	LDR	r11, =$data
	MOV     r11, r11, lsl #4	; [7:4]
  	STR	r11, [r10]
    	MEND
   
;---------------------------------------------------------------------------


; External Variables 

; External Functions 

; Global Variables 
 
; Local Variables 
 
; Local Functions 

        IMPORT  KernelStart

        TEXTAREA
        
        ; Include memory configuration file with g_oalAddressTable

;-------------------------------------------------------------------------------
;   Function: Startup
;
;   Main entry point for CPU initialization.
;

        INCLUDE oemaddrtab_cfg.inc

	LEAF_ENTRY      StartUp
    
	; Jump over power-off code. 
1	b		ResetHandler
	b %B1		;HandlerUndef	;handler for Undefined mode
	b %B1		;HandlerSWI		;handler for SWI interrupt
	b %B1		;HandlerPabort	;handler for PAbort
	b %B1		;HandlerDabort	;handler for DAbort
	b %B1		;				;reserved
	b %B1		;HandlerIRQ		;handler for IRQ interrupt 
	b %B1		;HandlerFIQ		;handler for FIQ interrupt


    
ResetHandler

	
	ldr		r0,=WTCON			;	Disable WatchDog.
	mov		r1,#0
	str		r1,[r0]

	ldr	r0, =BANK_CFG		; EBI
	ldr	r1, =BANK_CFG_VAL			; Refer s3c2413.inc
	str	r1,[r0]

	ldr     r0, = GPFCON
	ldr     r1, = 0x5500      
	str     r1, [r0]

	ldr     r0, = INTMSK
	ldr     r1, = 0xffffffff		; disable all interrupts
	str     r1, [r0]

	ldr     r0, = INTSUBMSK
	ldr     r1, = 0x7fff		     ; disable all sub interrupt
	str     r1, [r0]

	ldr     r0, = INTMOD
	mov		r1, #0x0			; set all interrupt as IRQ
	str     r1, [r0]


 LED_ON	~0x2
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; When the Eboot is already, No need to set again.
;; IF set as "FALSE", The FCLK,HCLK,PCLK Clock will detect automatically in OS.
;; IF set as "TRUE", The FCLK,HCLK,PCLK Clock and Memory setting will be set again here and detect automatically in OS.

 	[ CHANGE_CLK_OAL=1	; Refer the S3c2413.inc.

 LED_ON	~0x3

	ldr		r0,=CLKDIVN			;	Set Clock Divider
	ldr		r1,[r0]
	bic		r1,r1,#0xf		
	ldr		r2,=((Startup_USB48div<<6)+(Startup_ARMCLKdiv<<3)+(Startup_PCLKdiv<<2)+(Startup_HCLKdiv)) 
	orr		r1,r1,r2
	str		r1,[r0]			

 LED_ON	~0x4
  	ldr		r0,=UPLLCON			;	Set UPLL
	ldr		r1,=((0<<20)+(Startup_UMdiv<<12)+(Startup_UPdiv<<4)+(Startup_USdiv))
	str		r1,[r0]			

	ldr		r0,=MPLLCON			;	Set MPLL
	ldr		r1,=((0<<20)+(Startup_Mdiv<<12)+(Startup_Pdiv<<4)+(Startup_Sdiv))
	str		r1,[r0]			

	
 LED_ON	~0x5
	ldr		r0,=CLKSRC			;	Select MPLL clock out for SYSCLK
	ldr		r1,[r0]
	orr		r1,r1,#0x30			; Set MPLL=FCOUTmpll, UPLL=FOUTupll
	str		r1,[r0]			

 LED_ON	~0x6
	bl		InitMEM
	
 LED_ON	~0x7

	bl		InitSSMC				
	]	; End of PLL setting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

 LED_ON	~0x9

; Hardware setting end.	
;==================================================================

	;bl	loop_led


	
	add		r0, pc, #g_oalAddressTable - (. + 8)

	bl		KernelStart	; Call the WinCE kernel.


        ENTRY_END 








	LEAF_ENTRY OALCPUPowerOff

;       1. Push SVC state onto our stack
	stmdb   sp!, {r4-r12}                   
	stmdb   sp!, {lr}

;       2. Save MMU & CPU Register to RAM
    ldr     r3, =SLEEPDATA_BASE_VIRTUAL     ; base of Sleep mode storage

	ldr     r2, =Awake_address              ; store Virtual return address
	str     r2, [r3], #4

	mrc     p15, 0, r2, c1, c0, 0           ; load r2 with MMU Control
	ldr     r0, =MMU_CTL_MASK               ; mask off the undefined bits
	bic     r2, r2, r0
	str     r2, [r3], #4                    ; store MMU Control data

	mrc     p15, 0, r2, c2, c0, 0           ; load r2 with TTB address.
	ldr     r0, =MMU_TTB_MASK               ; mask off the undefined bits
	bic     r2, r2, r0
	str     r2, [r3], #4                    ; store TTB address

	mrc     p15, 0, r2, c3, c0, 0           ; load r2 with domain access control.
	str     r2, [r3], #4                    ; store domain access control

	str     sp, [r3], #4                    ; store SVC stack pointer

	mrs     r2, spsr
	str     r2, [r3], #4                    ; store SVC status register

	mov     r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Enter FIQ mode, no interrupts
	msr     cpsr, r1
	mrs     r2, spsr
	stmia   r3!, {r2, r8-r12, sp, lr}       ; store the FIQ mode registers

	mov     r1, #Mode_ABT:OR:I_Bit:OR:F_Bit ; Enter ABT mode, no interrupts
	msr     cpsr, r1
	mrs		r0, spsr
	stmia   r3!, {r0, sp, lr}               ; store the ABT mode Registers

	mov     r1, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; Enter IRQ mode, no interrupts
	msr     cpsr, r1
	mrs     r0, spsr
	stmia   r3!, {r0, sp, lr}               ; store the IRQ Mode Registers

	mov     r1, #Mode_UND:OR:I_Bit:OR:F_Bit ; Enter UND mode, no interrupts
	msr     cpsr, r1
	mrs     r0, spsr
	stmia   r3!, {r0, sp, lr}               ; store the UND mode Registers

	mov     r1, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Enter SYS mode, no interrupts
	msr     cpsr, r1
	stmia   r3!, {sp, lr}                   ; store the SYS mode Registers

	mov     r1, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Back to SVC mode, no interrupts
	msr     cpsr, r1

      ;3. Interrupt Disable  & Wakeup Source Setting
	ldr     r0, =vINTBASE
	mvn     r2, #0
	str     r2, [r0, #oINTMSK]
	str     r2, [r0, #oSRCPND]
	str     r2, [r0, #oINTPND]
	ldr	r2,=0xfffffefe
	str     r2, [r0, #oINTMSK]

	[ {FALSE}
	ldr	r0,=vGPIOBASE
	ldr	r1,[r0,#oGPFCON]
	ldr	r2,=0xfffffffc
	and	r1,r1,r2
	orr	r1,r1,#(1<<1)
	str	r1,[r0,#oGPFCON]
	]
	[{TRUE}
	ldr	r0,=vGPIOBASE
	ldr	r1,[r0,#oEINTMASK]
	ldr	r2,=0xffffffff
	and	r1,r1,r2
	str	r1,[r0,#oEINTMASK]
	ldr	r2,=0xffffffff
	str	r2,[r0,#oEINTPEND]
	]
;       3. do Checksum on the Sleepdata
	ldr     r3, =SLEEPDATA_BASE_VIRTUAL	; get pointer to SLEEPDATA
	mov     r2, #0
	ldr     r0, =SLEEPDATA_SIZE		; get size of data structure (in words)
30
	ldr     r1, [r3], #4

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