📄 s2413addr.inc
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FRCPAT46 EQU (0x4d00016C) ;//FRC Pattern
FRCPAT47 EQU (0x4d000170) ;//FRC Pattern
FRCPAT48 EQU (0x4d000174) ;//FRC Pattern
FRCPAT49 EQU (0x4d000178) ;//FRC Pattern
FRCPAT50 EQU (0x4d00017C) ;//FRC Pattern
FRCPAT51 EQU (0x4d000180) ;//FRC Pattern
FRCPAT52 EQU (0x4d000184) ;//FRC Pattern
FRCPAT53 EQU (0x4d000188) ;//FRC Pattern
FRCPAT54 EQU (0x4d00018C) ;//FRC Pattern
FRCPAT55 EQU (0x4d000190) ;//FRC Pattern
FRCPAT56 EQU (0x4d000194) ;//FRC Pattern
FRCPAT57 EQU (0x4d000198) ;//FRC Pattern
FRCPAT58 EQU (0x4d00019C) ;//FRC Pattern
FRCPAT59 EQU (0x4d0001A0) ;//FRC Pattern
FRCPAT60 EQU (0x4d0001A4) ;//FRC Pattern
FRCPAT61 EQU (0x4d0001A8) ;//FRC Pattern
FRCPAT62 EQU (0x4d0001AC) ;//FRC Pattern
FRCPAT63 EQU (0x4d0001B0) ;//FRC Pattern
LCDTEST EQU (0x4d0001B4) ;//FRC Pattern
;=================
; NAND flash
;=================
NFCONF EQU 0x4E000000 ;//NAND Flash configuration
NFCONT EQU 0x4E000004 ;//NAND Flash control
NFCMD EQU 0x4E000008 ;//NAND Flash command
NFADDR EQU 0x4E00000C ;//NAND Flash address
NFDATA EQU 0x4E000010 ;//NAND Flash data
NFMECCD0 EQU 0x4E000014 ;//NAND Flash ECC for Main
NFMECCD1 EQU 0x4E000018 ;//NAND Flash ECC for Main
NFSECCD EQU 0x4E00001C ;//NAND Flash ECC for Spare Area
NFSBLK EQU 0x4E000020 ;//NAND Flash programmable start block address
NFEBLK EQU 0x4E000024 ;//NAND Flash programmable end block address
NFSTAT EQU 0x4E000028 ;//NAND Flash operation status
NFECCERR0 EQU 0x4E00002C ;//NAND Flash ECC Error Status for I/O [7:0]
NFECCERR1 EQU 0x4E000030 ;//NAND Flash ECC Error Status for I/O [15:8]
NFMECC0 EQU 0x4E000034 ;//SLC or MLC NAND Flash ECC status
NFMECC1 EQU 0x4E000038 ;//SLC or MLC NAND Flash ECC status
NFSECC EQU 0x4E00003C ;//NAND Flash ECC for I/O[15:0]
NFMLCBITPT EQU 0x4E000040 ;//NAND Flash 4-bit ECC Error Pattern for data[7:0]
;=================
; Camera Interface
;=================
CISRCFMT EQU (0x4D800000) ;//Input Source Format
CIWDOFST EQU (0x4D800004) ;//Window offset
CIGCTRL EQU (0x4D800008) ;//Global control
CIFCTRL1 EQU (0x4D80000C) ;//flash control 1
CIFCTRL2 EQU (0x4D800010) ;//flash control 2
CIDOWSFT2 EQU (0x4D800014) ;//Window option 2
CICOYSA1 EQU (0x4D800018) ;//Y1 frame start address for codec DMA
CICOYSA2 EQU (0x4D80001C) ;//Y2 frame start address for codec DMA
CICOYSA3 EQU (0x4D800020) ;//Y3 frame start address for codec DMA
CICOYSA4 EQU (0x4D800024) ;//Y4 frame start address for codec DMA
CICOCBSA1 EQU (0x4D800028) ;//Cb1 frame start address for codec DMA
CICOCBSA2 EQU (0x4D80002C) ;//Cb2 frame start address for codec DMA
CICOCBSA3 EQU (0x4D800030) ;//Cb3 frame start address for codec DMA
CICOCBSA4 EQU (0x4D800034) ;//Cb4 frame start address for codec DMA
CICOCRSA1 EQU (0x4D800038) ;//Cr1 frame start address for codec DMA
CICOCRSA2 EQU (0x4D80003C) ;//Cr2 frame start address for codec DMA
CICOCRSA3 EQU (0x4D800040) ;//Cr3 frame start address for codec DMA
CICOCRSA4 EQU (0x4D800044) ;//Cr4 frame start address for codec DMA
CICOTRGFMT EQU (0x4D800048) ;//Target image format of codex DMA
CICOCTRL EQU (0x4D80004C) ;//Codec DMA comtrol
CICOSCPRERATIO EQU (0x4D800050) ;//Codec pre-scaler ratio control
CICOSCPREDST EQU (0x4D800054) ;//Codec pre-scaler desitination format
CICOSCCTRL EQU (0x4D800058) ;//Codec main-scaler control
CICOTAREA EQU (0x4D80005C) ;//Codec pre-scaler desination format
CICOSTATUS EQU (0x4D800064) ;//Codec path status
CIIMGCPT EQU (0x4D8000A0) ;//Imahe capture enable command
CICOCPTSEQ EQU (0x4D8000A4) ;//Codec dma capture sequence related
CICOSCOS EQU (0x4D8000A8) ;//Codec scan line offset related
CIIMGEFF EQU (0x4D8000B0) ;//Imahe Effects related
;=================
; UART
;=================
ULCON0 EQU (0x50000000) ;//UART channel 0 Line control
UCON0 EQU (0x50000004) ;//UART channel 0 Control
UFCON0 EQU (0x50000008) ;//UART channel 0 FIFO control
UMCON0 EQU (0x5000000c) ;//UART channel 0 Modem control
UTRSTAT0 EQU (0x50000010) ;//UART channel 0 Tx/Rx status
UERSTAT0 EQU (0x50000014) ;//UART channel 0 Rx error status
UFSTAT0 EQU (0x50000018) ;//UART channel 0 FIFO status
UMSTAT0 EQU (0x5000001c) ;//UART channel 0 Modem status
UBRDIV0 EQU (0x50000028) ;//UART Baud rate divisor 0
UDIVSLOT0 EQU (0x5000002c) ;//UART Baud rate dicisor 0
ULCON1 EQU (0x50004000) ;//UART channel 1 Line control
UCON1 EQU (0x50004004) ;//UART channel 1 Control
UFCON1 EQU (0x50004008) ;//UART channel 1 FIFO control
UMCON1 EQU (0x5000400c) ;//UART channel 1 Modem control
UTRSTAT1 EQU (0x50004010) ;//UART channel 1 Tx/Rx status
UERSTAT1 EQU (0x50004014) ;//UART channel 1 Rx error status
UFSTAT1 EQU (0x50004018) ;//UART channel 1 FIFO status
UMSTAT1 EQU (0x5000401c) ;//UART channel 1 Modem status
UBRDIV1 EQU (0x50004028) ;//UART Baud rate divisor 1
UDIVSLOT1 EQU (0x5000402c) ;//UART Baud rate divisor 1
ULCON2 EQU (0x50008000) ;//UART channel 2 Line control
UCON2 EQU (0x50008004) ;//UART channel 2 Control
UFCON2 EQU (0x50008008) ;//UART channel 2 FIFO control
UTRSTAT2 EQU (0x50008010) ;//UART channel 2 Tx/Rx status
UERSTAT2 EQU (0x50008014) ;//UART channel 2 Rx error status
UFSTAT2 EQU (0x50008018) ;//UART channel 2 FIFO status
UBRDIV2 EQU (0x50008028) ;//UART Baud rate divisor 2
UDIVSLOT2 EQU (0x5000802c) ;//UART Baud rate divisor 2
[ BIG_ENDIAN__
UTXH0 EQU 0x50000023 ;UART 0 Transmission Hold
URXH0 EQU 0x50000027 ;UART 0 Receive buffer
UTXH1 EQU 0x50004023 ;UART 1 Transmission Hold
URXH1 EQU 0x50004027 ;UART 1 Receive buffer
UTXH2 EQU 0x50008023 ;UART 2 Transmission Hold
URXH2 EQU 0x50008027 ;UART 2 Receive buffer
| ;Little Endian
UTXH0 EQU 0x50000020 ;UART 0 Transmission Hold
URXH0 EQU 0x50000024 ;UART 0 Receive buffer
UTXH1 EQU 0x50004020 ;UART 1 Transmission Hold
URXH1 EQU 0x50004024 ;UART 1 Receive buffer
UTXH2 EQU 0x50008020 ;UART 2 Transmission Hold
URXH2 EQU 0x50008024 ;UART 2 Receive buffer
]
;=================
; PWM TIMER
;=================
TCFG0 EQU 0x51000000 ;Timer 0 configuration
TCFG1 EQU 0x51000004 ;Timer 1 configuration
TCON EQU 0x51000008 ;Timer control
TCNTB0 EQU 0x5100000c ;Timer count buffer 0
TCMPB0 EQU 0x51000010 ;Timer compare buffer 0
TCNTO0 EQU 0x51000014 ;Timer count observation 0
TCNTB1 EQU 0x51000018 ;Timer count buffer 1
TCMPB1 EQU 0x5100001c ;Timer compare buffer 1
TCNTO1 EQU 0x51000020 ;Timer count observation 1
TCNTB2 EQU 0x51000024 ;Timer count buffer 2
TCMPB2 EQU 0x51000028 ;Timer compare buffer 2
TCNTO2 EQU 0x5100002c ;Timer count observation 2
TCNTB3 EQU 0x51000030 ;Timer count buffer 3
TCMPB3 EQU 0x51000034 ;Timer compare buffer 3
TCNTO3 EQU 0x51000038 ;Timer count observation 3
TCNTB4 EQU 0x5100003c ;Timer count buffer 4
TCNTO4 EQU 0x51000040 ;Timer count observation 4
;=================
; USB DEVICE
;=================
[ BIG_ENDIAN__
FUNC_ADDR_REG EQU 0x52000143 ;Function address
PWR_REG EQU 0x52000147 ;Power management
EP_INT_REG EQU 0x5200014b ;EP Interrupt pending and clear
USB_INT_REG EQU 0x5200015b ;USB Interrupt pending and clear
EP_INT_EN_REG EQU 0x5200015f ;Interrupt enable
USB_INT_EN_REG EQU 0x5200016f
FRAME_NUM1_REG EQU 0x52000173 ;Frame number lower byte
FRAME_NUM2_REG EQU 0x52000177 ;Frame number lower byte
INDEX_REG EQU 0x5200017b ;Register index
MAXP_REG EQU 0x52000183 ;Endpoint max packet
EP0_CSR EQU 0x52000187 ;Endpoint 0 status
IN_CSR1_REG EQU 0x52000187 ;In endpoint control status
IN_CSR2_REG EQU 0x5200018b
OUT_CSR1_REG EQU 0x52000193 ;Out endpoint control status
OUT_CSR2_REG EQU 0x52000197
OUT_FIFO_CNT1_REG EQU 0x5200019b ;Endpoint out write count
OUT_FIFO_CNT2_REG EQU 0x5200019f
EP0_FIFO EQU 0x520001c3 ;Endpoint 0 FIFO
EP1_FIFO EQU 0x520001c7 ;Endpoint 1 FIFO
EP2_FIFO EQU 0x520001cb ;Endpoint 2 FIFO
EP3_FIFO EQU 0x520001cf ;Endpoint 3 FIFO
EP4_FIFO EQU 0x520001d3 ;Endpoint 4 FIFO
EP1_DMA_CON EQU 0x52000203 ;EP1 DMA interface control
EP1_DMA_UNIT EQU 0x52000207 ;EP1 DMA Tx unit counter
EP1_DMA_FIFO EQU 0x5200020b ;EP1 DMA Tx FIFO counter
EP1_DMA_TTC_L EQU 0x5200020f ;EP1 DMA total Tx counter
EP1_DMA_TTC_M EQU 0x52000213
EP1_DMA_TTC_H EQU 0x52000217
EP2_DMA_CON EQU 0x5200021b ;EP2 DMA interface control
EP2_DMA_UNIT EQU 0x5200021f ;EP2 DMA Tx unit counter
EP2_DMA_FIFO EQU 0x52000223 ;EP2 DMA Tx FIFO counter
EP2_DMA_TTC_L EQU 0x52000227 ;EP2 DMA total Tx counter
EP2_DMA_TTC_M EQU 0x5200022b
EP2_DMA_TTC_H EQU 0x5200022f
EP3_DMA_CON EQU 0x52000243 ;EP3 DMA interface control
EP3_DMA_UNIT EQU 0x52000247 ;EP3 DMA Tx unit counter
EP3_DMA_FIFO EQU 0x5200024b ;EP3 DMA Tx FIFO counter
EP3_DMA_TTC_L EQU 0x5200024f ;EP3 DMA total Tx counter
EP3_DMA_TTC_M EQU 0x52000253
EP3_DMA_TTC_H EQU 0x52000257
EP4_DMA_CON EQU 0x5200025b ;EP4 DMA interface control
EP4_DMA_UNIT EQU 0x5200025f ;EP4 DMA Tx unit counter
EP4_DMA_FIFO EQU 0x52000263 ;EP4 DMA Tx FIFO counter
EP4_DMA_TTC_L EQU 0x52000267 ;EP4 DMA total Tx counter
EP4_DMA_TTC_M EQU 0x5200026b
EP4_DMA_TTC_H EQU 0x5200026f
| ; Little Endian
FUNC_ADDR_REG EQU 0x52000140 ;Function address
PWR_REG EQU 0x52000144 ;Power management
EP_INT_REG EQU 0x52000148 ;EP Interrupt pending and clear
USB_INT_REG EQU 0x52000158 ;USB Interrupt pending and clear
EP_INT_EN_REG EQU 0x5200015c ;Interrupt enable
USB_INT_EN_REG EQU 0x5200016c
FRAME_NUM1_REG EQU 0x52000170 ;Frame number lower byte
FRAME_NUM2_REG EQU 0x52000174 ;Frame number lower byte
INDEX_REG EQU 0x52000178 ;Register index
MAXP_REG EQU 0x52000180 ;Endpoint max packet
EP0_CSR EQU 0x52000184 ;Endpoint 0 status
IN_CSR1_REG EQU 0x52000184 ;In endpoint control status
IN_CSR2_REG EQU 0x52000188
OUT_CSR1_REG EQU 0x52000190 ;Out endpoint control status
OUT_CSR2_REG EQU 0x52000194
OUT_FIFO_CNT1_REG EQU 0x52000198 ;Endpoint out write count
OUT_FIFO_CNT2_REG EQU 0x5200019c
EP0_FIFO EQU 0x520001c0 ;Endpoint 0 FIFO
EP1_FIFO EQU 0x520001c4 ;Endpoint 1 FIFO
EP2_FIFO EQU 0x520001c8 ;Endpoint 2 FIFO
EP3_FIFO EQU 0x520001cc ;Endpoint 3 FIFO
EP4_FIFO EQU 0x520001d0 ;Endpoint 4 FIFO
EP1_DMA_CON EQU 0x52000200 ;EP1 DMA interface control
EP1_DMA_UNIT EQU 0x52000204 ;EP1 DMA Tx unit counter
EP1_DMA_FIFO EQU 0x52000208 ;EP1 DMA Tx FIFO counter
EP1_DMA_TTC_L EQU 0x5200020c ;EP1 DMA total Tx counter
EP1_DMA_TTC_M EQU 0x52000210
EP1_DMA_TTC_H EQU 0x52000214
EP2_DMA_CON EQU 0x52000218 ;EP2 DMA interface control
EP2_DMA_UNIT EQU 0x5200021c ;EP2 DMA Tx unit counter
EP2_DMA_FIFO EQU 0x52000220 ;EP2 DMA Tx FIFO counter
EP2_DMA_TTC_L EQU 0x52000224 ;EP2 DMA total Tx counter
EP2_DMA_TTC_M EQU 0x52000228
EP2_DMA_TTC_H EQU 0x5200022c
EP3_DMA_CON EQU 0x52000240 ;EP3 DMA interface control
EP3_DMA_UNIT EQU 0x52000244 ;EP3 DMA Tx unit counter
EP3_DMA_FIFO EQU 0x52000248 ;EP3 DMA Tx FIFO counter
EP3_DMA_TTC_L EQU 0x5200024c ;EP3 DMA total Tx counter
EP3_DMA_TTC_M EQU 0x52000250
EP3_DMA_TTC_H EQU 0x52000254
EP4_DMA_CON EQU 0x52000258 ;EP4 DMA interface control
EP4_DMA_UNIT EQU 0x5200025c ;EP4 DMA Tx unit counter
EP4_DMA_FIFO EQU 0x52000260 ;EP4 DMA Tx FIFO counter
EP4_DMA_TTC_L EQU 0x52000264 ;EP4 DMA total Tx counter
EP4_DMA_TTC_M EQU 0x52000268
EP4_DMA_TTC_H EQU 0x5200026c
]
;=================
; WATCH DOG TIMER
;=================
WTCON EQU 0x53000000 ;Watch-dog timer mode
WTDAT EQU 0x53000004 ;Watch-dog timer data
WTCNT EQU 0x53000008 ;Eatch-dog timer count
;=================
; IIC
;=================
IICCON EQU 0x54000000 ;IIC control
IICSTAT EQU 0x54000004 ;IIC status
IICADD EQU 0x54000008 ;IIC address
IICDS EQU 0x5400000c ;IIC data shift
;=================
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