usb.c

支持三星原产的S3C2413开发板

			WrPktEp0((U8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE); 
			SET_EP0_IN_PKT_RDY();
			ep0State=EP0_STATE_GD_STR_I2;
			ep0SubState++;
		}
		else
		{
			WrPktEp0((U8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),
			sizeof(descStr2)-(ep0SubState*EP0_PKT_SIZE)); 
			SET_EP0_INPKTRDY_DATAEND();
			ep0State=EP0_STATE_INIT;     
			ep0SubState=0;
		}
		break;

	case EP0_CONFIG_SET:
		WrPktEp0((U8 *)&ConfigSet+0,1); 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS0:
		WrPktEp0((U8 *)&StatusGet+0,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS1:
		WrPktEp0((U8 *)&StatusGet+1,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS2:
		WrPktEp0((U8 *)&StatusGet+2,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS3:
		WrPktEp0((U8 *)&StatusGet+3,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS4:
		WrPktEp0((U8 *)&StatusGet+4,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	default:
//		DbgPrintf("UE:G?D");
		EdbgOutputDebugString("[UE:G?D]\r\n");
		break;
	}
}

void ReconfigUsbd(void)
{
// *** End point information ***
//   EP0: control
//   EP1: bulk in end point
//   EP2: not used
//   EP3: bulk out end point
//   EP4: not used
    
	pUSBCtrlAddr->PMR.sus_en = 0;
	pUSBCtrlAddr->PMR.sus_mo = 0;
	pUSBCtrlAddr->PMR.mcu_res = 0;
	pUSBCtrlAddr->PMR.usb_re = 0;
	//pUSBCtrlAddr->PMR.iso_up = 0;

	pUSBCtrlAddr->INDEX.index = 0;
	pUSBCtrlAddr->MAXP.maxp = 0x01;	//EP0 max packit size = 8 
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->EP0ICSR1.sse_ = 1;
	//EP0:clear OUT_PKT_RDY & SETUP_END

	pUSBCtrlAddr->INDEX.index = 1;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP1 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 1;
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->INDEX.index = 2;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP2 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 1;
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->INDEX.index = 3;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP3 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 0;
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 0;
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	//clear OUT_PKT_RDY, data_toggle_bit.
	//The data toggle bit should be cleared when initialization.
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->INDEX.index = 4;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP4 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 0;
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	//clear OUT_PKT_RDY, data_toggle_bit.
	//The data toggle bit should be cleared when initialization.
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->EIR.ep0_int=1;
	pUSBCtrlAddr->EIR.ep1_int=1;
	pUSBCtrlAddr->EIR.ep2_int=1;
	pUSBCtrlAddr->EIR.ep3_int=1;
	pUSBCtrlAddr->EIR.ep4_int=1;
	pUSBCtrlAddr->UIR.reset_int = 1;
	pUSBCtrlAddr->UIR.sus_int = 1;
	pUSBCtrlAddr->UIR.resume_int = 1;

	//Clear all usbd pending bits

	//EP0,1,3 & reset interrupt are enabled
	pUSBCtrlAddr->EIER.ep0_int_en = 1;
	pUSBCtrlAddr->EIER.ep1_int_en = 1;
	pUSBCtrlAddr->EIER.ep3_int_en = 1;

	pUSBCtrlAddr->UIER.reset_int_en = 1;
	ep0State=EP0_STATE_INIT;

}

#define    BIT_ALLMSK       (0xffffffff)
#define    BIT_USBD         (0x1<<25)
#define    BIT_DMA2         (0x1<<19)

void Isr_Init(void)
{
    volatile S3C2413_INTR_REG *s2413INT = (S3C2413_INTR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_INTR, FALSE);

	s2413INT->INTMOD=0x0;	  // All=IRQ mode
	s2413INT->INTMSK=BIT_ALLMSK;	  // All interrupt is masked.

	EdbgOutputDebugString("INFO: (unsigned)IsrUsbd : 0x%x\r\n", (unsigned)IsrUsbd);
	EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%x\r\n", (unsigned)IsrHandler);

	// make value to assemble code "b IsrHandler"
	pISR =(unsigned)(0xEA000000)+(((unsigned)IsrHandler - (0x80000000 + 0x18 + 0x8) )>>2);

	s2413INT->SRCPND  = BIT_USBD;
	if (s2413INT->INTPND & BIT_USBD) s2413INT->INTPND |= BIT_USBD;
	s2413INT->INTMSK &= ~BIT_USBD;		// USB Interrupt enable.

	s2413INT->SRCPND  = BIT_DMA2;
	if (s2413INT->INTPND & BIT_DMA2) s2413INT->INTPND = BIT_DMA2;
	s2413INT->INTMSK &= ~BIT_DMA2;		// DMA Interrupt enable.
}

void IsrUsbd(unsigned int val)
{
    U8 saveIndexReg=pUSBCtrlAddr->INDEX.index;
    volatile S3C2413_INTR_REG *s2413INT = (S3C2413_INTR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_INTR, FALSE);
    volatile S3C2413_CLKPWR_REG *s2413PWR = (S3C2413_CLKPWR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_CLOCK_POWER, FALSE);

#if 0
	EdbgOutputDebugString("INFO : IsrUsbd : Interrupt occurred \r\n");
	EdbgOutputDebugString("INFO : s2413INT->SRCPND = 0x%x \r\n", s2413INT->SRCPND);
	EdbgOutputDebugString("INFO : s2413INT->INTMSK = 0x%x \r\n", s2413INT->INTMSK);
	EdbgOutputDebugString("INFO : s2413INT->INTPND = 0x%x \r\n", s2413INT->INTPND);
	EdbgOutputDebugString("INFO : s2413PWR->CLKCON = 0x%x \r\n", s2413PWR->CLKCON);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr = 0x%x \r\n", pUSBCtrlAddr);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep0_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep0_int_en);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep1_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep1_int_en);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep2_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep2_int_en);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep3_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep3_int_en);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep4_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep4_int_en);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep0_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep0_int);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep1_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep1_int);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep2_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep2_int);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep3_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep3_int);
	EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep4_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep4_int);
	EdbgOutputDebugString("\r\n");
#endif
	

	if (s2413INT->INTPND & BIT_DMA2)
	{
		DMA2Handler();
		goto Exit;
	}

    if(pUSBCtrlAddr->UIR.sus_int)
    {
		pUSBCtrlAddr->UIR.sus_int = 1;
		//EdbgOutputDebugString("<SUS]\r\n");
    }
    if(pUSBCtrlAddr->UIR.resume_int)
    {
		pUSBCtrlAddr->UIR.resume_int = 1;
		//EdbgOutputDebugString("<RSM]\r\n");
    }
    if(pUSBCtrlAddr->UIR.reset_int)
    {
		//EdbgOutputDebugString("<RSET]\r\n");
		ReconfigUsbd();
		pUSBCtrlAddr->UIR.reset_int = 1;
		PrepareEp1Fifo(); 
    }

    if(pUSBCtrlAddr->EIR.ep0_int)
    {
		//EdbgOutputDebugString("EP0 Interrupt\r\n");
		pUSBCtrlAddr->EIR.ep0_int=1;
    	Ep0Handler();
    }
    if(pUSBCtrlAddr->EIR.ep1_int)
    {
		//EdbgOutputDebugString("<1:TBD]\r\n");
		pUSBCtrlAddr->EIR.ep1_int=1;
    	Ep1Handler();
    }
    if(pUSBCtrlAddr->EIR.ep2_int)
    {
		pUSBCtrlAddr->EIR.ep2_int=1;
		//EdbgOutputDebugString("<2:TBD]\r\n");
    }
    if(pUSBCtrlAddr->EIR.ep3_int)
    {
		//EdbgOutputDebugString("<3:TBD]\r\n");
    	Ep3Handler();
		pUSBCtrlAddr->EIR.ep3_int=1;
    }
    if(pUSBCtrlAddr->EIR.ep4_int)
    {
		pUSBCtrlAddr->EIR.ep4_int=1;
		//EdbgOutputDebugString("<4:TBD]\r\n");
    }

	if (s2413INT->INTPND & BIT_USBD)
	{
		s2413INT->SRCPND  = BIT_USBD;
		if (s2413INT->INTPND & BIT_USBD) s2413INT->INTPND = BIT_USBD;
	}

Exit:
    pUSBCtrlAddr->INDEX.index=saveIndexReg;

}

void Ep3Handler(void)
{
    int fifoCnt;
    volatile S3C2413_INTR_REG *s2413INT = (S3C2413_INTR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_INTR, FALSE);

    pUSBCtrlAddr->INDEX.index=3;

    if(pUSBCtrlAddr->OCSR1.out_pkt_rdy)
    {
		fifoCnt=pUSBCtrlAddr->OFCR1.out_cnt_low;

		downPt = (LPBYTE)(downPtIndex);
		RdPktEp3((U8 *)downPt,fifoCnt);
		downPtIndex += 64;
		s2413INT->INTMSK |= BIT_USBD;		// USB Interrupt disable.
		return;
    }

    //I think that EPO_SENT_STALL will not be set to 1.
    if(pUSBCtrlAddr->OCSR1.sent_stall)
    {
	   	CLR_EP3_SENT_STALL();
   		return;
    }
}

void DMA2Handler(void)
{
    volatile S3C2413_INTR_REG *s2413INT = (S3C2413_INTR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_INTR, FALSE);
    volatile S3C2413_DMA_REG *v_pDMAregs = (S3C2413_DMA_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_DMA, FALSE);

	s2413INT->SRCPND  = BIT_DMA2;
	if (s2413INT->INTPND & BIT_DMA2) s2413INT->INTPND = BIT_DMA2;

	//EdbgOutputDebugString("INFO : DMA2handler\r\n");
	while ( !(v_pDMAregs ->DSTAT2 & 0xfffff)) ;
	downPtIndex += 0x80000;

	v_pDMAregs->DIDST2=((U32)downPtIndex+0x80000);
	//v_pDMAregs->DIDSTC2=(1<<2)|(0<<1)|(0<<0);  
	//v_pDMAregs->DCON2=v_pDMAregs->DCON2&~(0xfffff)|(0x80000); 
	v_pDMAregs->DIDSTC2=(0<<1)|(0<<0);
	v_pDMAregs->DCON2=v_pDMAregs->DCON2&~(0xfffff)|(0x80000);  // Half Word


	while(rEP3_DMA_TTC<0xfffff)
	{
		pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
		pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
		pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
	}
}

void ConfigEp3DmaMode(U32 bufAddr,U32 count)
{
    volatile S3C2413_INTR_REG *s2413INT = (S3C2413_INTR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_INTR, FALSE);
    volatile S3C2413_DMA_REG *v_pDMAregs = (S3C2413_DMA_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_DMA, FALSE);
	int i;

	EdbgOutputDebugString("INFO : Write Count 0x%x\r\n", count);

	pUSBCtrlAddr->INDEX.index=3;
	count=count&0xfffff; //transfer size should be <1MB
	v_pDMAregs->DISRCC2=(1<<1)|(1<<0);	// LOC=1:APB, INC:1:fixed.
	v_pDMAregs->DISRC2=REAL_PHYSICAL_ADDR_EP3_FIFO; //src=APB,fixed,src=EP3_FIFO
	v_pDMAregs->DIDSTC2=(0<<1)|(0<<0);	// LOC=0:AHB, INC:0:Increment
	v_pDMAregs->DIDST2=bufAddr;       //dst=AHB,increase,dst=bufAddr
	//v_pDMAregs->DCON2=(count)|(1<<31)|(0<<30)|(1<<29)|(0<<28)|(0<<27)|(4<<24)|(1<<23)|(0<<22)|(0<<20); 
	v_pDMAregs->DCON2=(count)|(1<<31)|(0<<30)|(1<<29)|(0<<28)|(0<<27)|(1<<23)|(0<<22)|(0<<20); 
	//v_pDMAregs->DMAREQSEL2 = DMAREQSEL_USB_EP3|(1<<0); 	// USB device EP3., H/W sel.
	v_pDMAregs->DMAREQSEL2 = (15<<1)|(1<<0); 	// USB device EP3., H/W sel.
	//handshake,requestor=APB,CURR_TC int enable,unit transfer,
	//single service,src=USBD,H/W request,autoreload,byte,CURR_TC

	v_pDMAregs->DMASKTRIG2 = (1<<1);
	//DMA 2 on

	pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
	pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
	pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;

	pUSBCtrlAddr->OCSR2.auto_clr = 1;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
	//AUTO_CLR(OUT_PKT_READY is cleared automatically), interrupt_masking.
	pUSBCtrlAddr->EP3DU.ep3_unit_cnt = 1;

	*(volatile BYTE *)&pUSBCtrlAddr->EP3DC=UDMA_OUT_DMA_RUN|UDMA_DMA_MODE_EN;

	// deamnd disable,out_dma_run=run,in_dma_run=stop,DMA mode enable
    //wait until DMA_CON is effective.
	*(volatile BYTE *)&pUSBCtrlAddr->EP3DC;
	for(i=0;i<10;i++);
}

void ConfigEp3IntMode(void)
{
    volatile S3C2413_DMA_REG *v_pDMAregs = (S3C2413_DMA_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_DMA, FALSE);
    pUSBCtrlAddr->INDEX.index=3;
    
    v_pDMAregs->DMASKTRIG2= (0<<1);  // EP3=DMA ch 2
        //DMA channel off
	pUSBCtrlAddr->OCSR2.auto_clr = 0;

	//AUTOCLEAR off,interrupt_enabled (???)
	pUSBCtrlAddr->EP3DU.ep3_unit_cnt = 1;
	*(volatile BYTE *)&pUSBCtrlAddr->EP3DC=0x0;
    //wait until DMA_CON is effective.
    *(volatile BYTE *)&pUSBCtrlAddr->EP3DC;
}

#pragma optimize ("",off)
BOOL UbootReadData(DWORD cbData, LPBYTE pbData)
{
    volatile S3C2413_INTR_REG *s2413INT = (S3C2413_INTR_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_INTR, FALSE);
    volatile S3C2413_IOPORT_REG *s2413IOP = (S3C2413_IOPORT_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_IOPORT, FALSE);
    volatile S3C2413_DMA_REG *v_pDMAregs = (S3C2413_DMA_REG *)OALPAtoVA(S3C2413_BASE_REG_PA_DMA, FALSE);
	unsigned int temp;
	unsigned int i;

	//(UINT32)pbData = ((UINT32)pbData| (UINT32)0x20000000);
	//RETAILMSG(1,(TEXT("dcdst2 0x%x ,,, readptindex 0x%x ,,, cbData 0x%x ,,, pbData 0x%x\r\n"),v_pDMAregs->DCDST2 , readPtIndex+cbData, cbData,pbData));
Loop:
	if ( v_pDMAregs->DCDST2 > readPtIndex + cbData )
//	if ( downPtIndex > readPtIndex + cbData )
	{
		memcpy(pbData, readPtIndex + 0x70000000, cbData);
		readPtIndex += cbData;
		loopcnt = 0;
	}
	else if (loopcnt > 15)	// it may be
	{
		memcpy(pbData, readPtIndex, cbData);
		readPtIndex += cbData;
	}
	else if (downPtIndex == DMABUFFER)
	{
		while (downPtIndex == DMABUFFER) {};	// first 64 bytes, get interrupt mode.

		if ( readPtIndex == DMABUFFER )
		{
			memcpy(pbData, readPtIndex, cbData);
			readPtIndex += cbData;
		}

		s2413INT->SRCPND  = BIT_USBD;
		if (s2413INT->INTPND & BIT_USBD) s2413INT->INTPND = BIT_USBD;
		s2413INT->INTMSK |= BIT_USBD;		// USB Interrupt disable.

		// read data with DMA operation.
		s2413INT->SRCPND  = BIT_DMA2;
		if (s2413INT->INTPND & BIT_DMA2) s2413INT->INTPND = BIT_DMA2;
		s2413INT->INTMSK &= ~BIT_DMA2;		// DMA Interrupt enable.

		pUSBCtrlAddr->INDEX.index=3;
		CLR_EP3_OUT_PKT_READY();

		ConfigEp3DmaMode(downPtIndex,0x80000);

		v_pDMAregs->DIDST2=(downPtIndex+0x80000);	//for 1st autoreload.
		v_pDMAregs->DIDSTC2=(0<<1)|(0<<0);
		v_pDMAregs->DCON2=v_pDMAregs->DCON2&~(0xfffff)|(0x80000);

		while(rEP3_DMA_TTC<0xfffff)
		{
			pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
			pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
			pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
		}

		
		
	}
	else
	{
		//EdbgOutputDebugString(" v_pDMAregs->DCDST2 = 0x%x  readPtIndex + cbData = 0x%x\r\n",  v_pDMAregs->DCDST2 , readPtIndex + cbData);
		for (i = 0; i < 0x2ffff; i++ )
		{
		}
		loopcnt ++;
		EdbgOutputDebugString("INFO : UbootReadData : loopcnt = 0x%x\r\n", loopcnt);
		goto Loop;
	}

	return TRUE;
}
#pragma optimize ("",on)